公开(公告)号：US11729386B2

公开(公告)日：2023-08-15

申请号：US16911810

申请日：2020-06-25

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Masato Ohkawa ,  Hideo Saitou ,  Tadamasa Toma ,  Takahiro Nishi ,  Kiyofumi Abe ,  Ryuichi Kanoh

IPC: H04N19/12 ,  H04N19/124 ,  H04N19/176 ,  H04N19/625

CPC classification number: H04N19/12 ,  H04N19/124 ,  H04N19/176 ,  H04N19/625

Abstract: When a transform-basis adaptive selection mode is enabled, an encoder that transforms residuals of a current block to encode an image: adaptively selects a first horizontal transform basis from among one or more transform basis candidates when a horizontal size of the current block is greater than a first horizontal threshold size; otherwise selects a fixed horizontal transform basis as a first horizontal transform basis; adaptively selects a first vertical transform basis from among the one or more transform basis candidates when a vertical size of the current block is greater than a first vertical threshold size; otherwise selects a fixed vertical transform basis as a first vertical transform basis; and generates first transform coefficients by performing a first horizontal transform and a first vertical transform on the residuals of the current block, using the first horizontal transform basis selected and the first vertical transform basis selected, respectively.

公开(公告)号：US11722714B2

公开(公告)日：2023-08-08

申请号：US17554168

申请日：2021-12-17

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Noritaka Iguchi ,  Tadamasa Toma ,  Hisaya Katou

IPC: H04N21/236 ,  H04N19/169 ,  H04N19/436 ,  H04N19/70 ,  G10L19/16 ,  H04N5/38 ,  H04N5/44 ,  H04N21/434 ,  H04N21/854

CPC classification number: H04N21/23614 ,  G10L19/167 ,  H04N5/38 ,  H04N5/44 ,  H04N19/188 ,  H04N19/436 ,  H04N19/70 ,  H04N21/23605 ,  H04N21/4343 ,  H04N21/4348 ,  H04N21/85406

Abstract: A transmitting method according to one aspect of the present disclosure includes: encoding a video signal and generating encoded data including a plurality of access units; storing the plurality of access units in a packet in a unit that defines one access unit as one unit or in a unit defined by dividing one access unit, and generating a packet group; transmitting the generated packet group as data; generating first information and second information, the first information indicating a presentation time of a first access unit that is presented first among the plurality of access units, and the second information being used to calculate a decoding time of the plurality of access units; and transmitting the first information and the second information as control information.

公开(公告)号：US11722670B2

公开(公告)日：2023-08-08

申请号：US17886735

申请日：2022-08-12

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Kiyofumi Abe ,  Ryuichi Kanoh ,  Takahiro Nishi ,  Tadamasa Toma

IPC: H04N19/126 ,  H04N19/176 ,  H04N19/18 ,  H04N19/60 ,  H04N19/30 ,  H04N19/124

CPC classification number: H04N19/126 ,  H04N19/124 ,  H04N19/176 ,  H04N19/18 ,  H04N19/30 ,  H04N19/60

Abstract: Various embodiments provide an encoder that performs an up-conversion and a down-conversion on a first quantization matrix to generate a second quantization matrix, and quantizes transform coefficients of a current block using the second quantization matrix. The first quantization matrix has a first number of rows and a first number of columns equal to the first number of rows, and the second quantization matrix has a second number of rows and a second number of columns different from the second number of rows. In the up-conversion, the circuitry generates the second quantization matrix such that one of the second number of rows or the second number of columns is larger than the first number of rows. In the down-conversion, the circuitry generates the second quantization matrix such that the other of the second number of rows or the second number of columns is smaller than the first number of rows.

公开(公告)号：US11683492B2

公开(公告)日：2023-06-20

申请号：US17884420

申请日：2022-08-09

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Kiyofumi Abe ,  Ryuichi Kanoh ,  Takahiro Nishi ,  Tadamasa Toma

IPC: H04N19/126 ,  H04N19/176 ,  H04N19/18 ,  H04N19/60 ,  H04N19/30 ,  H04N19/124

CPC classification number: H04N19/126 ,  H04N19/124 ,  H04N19/176 ,  H04N19/18 ,  H04N19/30 ,  H04N19/60

Abstract: Various embodiments provide an encoder that performs an up-conversion and a down-conversion on a first quantization matrix to generate a second quantization matrix, and quantizes transform coefficients of a current block using the second quantization matrix. The first quantization matrix has a first number of rows and a first number of columns equal to the first number of rows, and the second quantization matrix has a second number of rows and a second number of columns different from the second number of rows. In the up-conversion, the circuitry generates the second quantization matrix such that one of the second number of rows or the second number of columns is larger than the first number of rows. In the down-conversion, the circuitry generates the second quantization matrix such that the other of the second number of rows or the second number of columns is smaller than the first number of rows.

公开(公告)号：US11665366B2

公开(公告)日：2023-05-30

申请号：US17867926

申请日：2022-07-19

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Chong Soon Lim ,  Hai Wei Sun ,  Sughosh Pavan Shashidhar ,  Han Boon Teo ,  Ru Ling Liao ,  Jing Ya Li ,  Tadamasa Toma ,  Takahiro Nishi ,  Kiyofumi Abe ,  Ryuichi Kanoh

IPC: H04N19/52

CPC classification number: H04N19/52

Abstract: An encoder which includes circuitry and memory. Using the memory, the circuitry generates a list which includes candidates for a first motion vector for a first partition. The list has a maximum list size and an order of the candidates, and at least one of the maximum list size or the order of the candidates is dependent on at least one of a partition size or a partition shape of the first partition. The circuitry selects the first motion vector from the candidates included in the list; encodes an index indicating the first motion vector among the candidates in the list into the bitstream based on the maximum list size; and generates the predicted image for the first partition using the first motion vector.

公开(公告)号：US20230115058A1

公开(公告)日：2023-04-13

申请号：US18071365

申请日：2022-11-29

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Jing Ya LI ,  Chong Soon LIM ,  Hai Wei SUN ,  Han Boon TEO ,  Che Wei KUO ,  Chu Tong WANG ,  Kiyofumi ABE ,  Takahiro Nishi ,  Tadamasa Toma ,  Yusuke KATO

IPC: H04N19/117 ,  H04N19/105 ,  H04N19/119 ,  H04N19/82 ,  H04N19/13 ,  H04N19/18 ,  H04N19/186 ,  H04N19/124

Abstract: An encoder includes circuitry and memory. The circuitry, in operation, generates a first coefficient value by applying a CCALF (cross component adaptive loop filtering) process to a first reconstructed image sample of a luma component. The circuitry generates a second coefficient value by applying an ALF (adaptive loop filtering) process to a second reconstructed image sample of a chroma component. The circuitry generates a third coefficient value by adding the first coefficient value to the second coefficient value, and encodes a third reconstructed image sample of the chroma component using the third coefficient value. In the CCALF process, in response to a coordinate of the second reconstructed image sample being (x, y), coordinates of the first reconstructed image samples are (2x, 2y−1), (2x−1, 2y), (2x, 2y), (2x+1, 2y), (2x−1, 2y+1), (2x, 2y+1), (2x+1, 2y+1), and (2x, 2y+2).

公开(公告)号：US11625863B2

公开(公告)日：2023-04-11

申请号：US16828059

申请日：2020-03-24

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Toshiyasu Sugio ,  Takahiro Nishi ,  Tadamasa Toma ,  Toru Matsunobu ,  Satoshi Yoshikawa ,  Tatsuya Koyama

IPC: G06T9/00 ,  G06T17/05 ,  H04N13/275 ,  H04L67/01 ,  G01C21/00 ,  G01S17/89 ,  G05D1/02

Abstract: A three-dimensional data creation method in a client device includes: creating three-dimensional data of a surrounding area of the client device using sensor information that is obtained through a sensor equipped in the client device and indicates a surrounding condition of the client device; estimating a self-location of the client device using the three-dimensional data created; and transmitting the sensor information obtained to a server or an other client device.

公开(公告)号：US11595654B2

公开(公告)日：2023-02-28

申请号：US17883445

申请日：2022-08-08

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Kiyofumi Abe ,  Ryuichi Kanoh ,  Takahiro Nishi ,  Tadamasa Toma

IPC: H04N19/126 ,  H04N19/176 ,  H04N19/18 ,  H04N19/60 ,  H04N19/30

Abstract: Various embodiments provide an encoder that performs an up-conversion and a down-conversion on a first quantization matrix to generate a second quantization matrix, and quantizes transform coefficients of a current block using the second quantization matrix. The first quantization matrix has a first number of rows and a first number of columns equal to the first number of rows, and the second quantization matrix has a second number of rows and a second number of columns different from the second number of rows. In the up-conversion, the circuitry generates the second quantization matrix such that one of the second number of rows or the second number of columns is larger than the first number of rows. In the down-conversion, the circuitry generates the second quantization matrix such that the other of the second number of rows or the second number of columns is smaller than the first number of rows.

公开(公告)号：US11582450B2

公开(公告)日：2023-02-14

申请号：US17227015

申请日：2021-04-09

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Ryuichi Kanoh ,  Takahiro Nishi ,  Tadamasa Toma ,  Kiyofumi Abe

IPC: H04N19/117 ,  H04N19/146 ,  H04N19/176

Abstract: A decoder comprises circuitry and memory. The circuitry, using the memory, in operation, determines a number of first pixels and a number of second pixels used in a deblocking filter process, wherein the first pixels are located at an upper side of a block boundary and the second pixels are located at a lower side of the block boundary, and performs the deblocking filter process on the block boundary. The number of the first pixels and the number of the second pixels are selected from among candidates, wherein the candidates include at least 4 and M larger than 4. Response to a location of the block boundary being a predetermined location, the number of the first pixels used in the deblocking filter process is limited to be 4.

公开(公告)号：US11575920B2

公开(公告)日：2023-02-07

申请号：US17509360

申请日：2021-10-25

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Takahiro Nishi ,  Tadamasa Toma ,  Kiyofumi Abe ,  Ryuichi Kanoh

IPC: H04N19/31 ,  H04N19/117 ,  H04N19/172

Abstract: An encoder which encodes a video including a plurality of pictures includes circuitry and memory. Using the memory, the circuitry performs: encoding a first picture among the plurality of pictures; and performing (i) a first operation for encoding a parameter set for a second picture which follows the first picture in coding order among the plurality of pictures after encoding the first picture, and encoding the second picture after encoding the parameter set, or (ii) a second operation for encoding the second picture without encoding the parameter set after encoding the first picture. The circuitry performs the first operation when the second picture is a determined picture, in the performing of the first operation or the second operation.