公开(公告)号：US20230152126A1

公开(公告)日：2023-05-18

申请号：US18155531

申请日：2023-01-17

Applicant: STMicroelectronics (Rousset) SAS ,  STMicroelectronics SA ,  STMicroelectronics (Grenoble 2) SAS

Inventor： Laurent Beyly ,  Oliver Richard ,  Kenichi OKU

IPC: G01D5/24 ,  H03K17/96

CPC classification number: G01D5/24 ,  H03K17/962 ,  H03K2217/9607

Abstract: An embodiment of the present disclosure relates to a method of detection of a touch contact by a sensor including a first step of comparison of a voltage with a first voltage threshold; and a second step of comparison of the voltage with a second voltage threshold, the second step being implemented if the first voltage threshold has been reached within a duration shorter than a first duration threshold, the second voltage threshold being higher than the first voltage threshold.

公开(公告)号：US11653582B2

公开(公告)日：2023-05-16

申请号：US16184246

申请日：2018-11-08

Applicant: STMicroelectronics (Crolles 2) SAS ,  STMicroelectronics (Grenoble 2) SAS ,  STMicroelectronics (Rousset) SAS

Inventor： Franck Arnaud ,  David Galpin ,  Stephane Zoll ,  Olivier Hinsinger ,  Laurent Favennec ,  Jean-Pierre Oddou ,  Lucile Broussous ,  Philippe Boivin ,  Olivier Weber ,  Philippe Brun ,  Pierre Morin

IPC: H01L45/00 ,  H01L27/24 ,  G11C13/00

CPC classification number: H10N70/8616 ,  G11C13/0004 ,  G11C13/0069 ,  H10B63/30 ,  H10B63/80 ,  H10N70/011 ,  H10N70/021 ,  H10N70/231 ,  H10N70/826 ,  H10N70/8265 ,  H10N70/8413 ,  H10N70/882 ,  G11C2013/008

Abstract: An electronic chip includes memory cells made of a phase-change material and a transistor. First and second vias extend from the transistor through an intermediate insulating layer to a same height. A first metal level including a first interconnection track in contact with the first via is located over the intermediate insulating layer. A heating element for heating the phase-change material is located on the second via, and the phase-change material is located on the heating element. A second metal level including a second interconnection track is located above the phase-change material. A third via extends from the phase-change material to the second interconnection track.

公开(公告)号：US11651064B2

公开(公告)日：2023-05-16

申请号：US16832966

申请日：2020-03-27

Applicant: STMICROELECTRONICS (ROUSSET) SAS ,  PROTON WORLD INTERNATIONAL N.V.

Inventor： Michael Peeters ,  Fabrice Marinet

IPC: G06F21/44 ,  G06F7/57 ,  G06F9/38

CPC classification number: G06F21/44 ,  G06F7/57 ,  G06F9/3818

Abstract: The disclosure includes a method of authenticating a processor that includes an arithmetic and logic unit. At least one decoded operand of at least a portion of a to-be-executed opcode is received on a first terminal of the arithmetic and logic unit. A signed instruction is received on a second terminal of the arithmetic and logic unit. The signed instruction combines a decoded instruction of the to-be-executed opcode and at least one previously-executed opcode.

公开(公告)号：US20230131067A1

公开(公告)日：2023-04-27

申请号：US17968163

申请日：2022-10-18

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Pierre Demaj ,  Laurent Folliot

IPC: G06N3/02 ,  G06K9/00

Abstract: According to one aspect, a method is proposed for detecting events or elements in physical signals by implementing an artificial neural network. The method includes an assessment of a probability of the presence of the event or the element by an implementation of the neural network. The implementation of the neural network according to a nominal mode takes as input a physical signal having a first resolution, called nominal resolution, when the probability of presence of the event or the element is greater than a threshold. The implementation of the neural network according to a low power mode takes as input a physical signal having a second resolution, called reduced resolution, lower than the first resolution, when the probability of presence of the event or the element is below the threshold.

公开(公告)号：US11637590B2

公开(公告)日：2023-04-25

申请号：US17364291

申请日：2021-06-30

Applicant: STMicroelectronics (Grenoble 2) SAS ,  STMicroelectronics (Rousset) SAS

Inventor： Sylvie Wuidart ,  Sophie Maurice

IPC: G05B11/01 ,  H04B5/00 ,  G06F21/60 ,  H04W88/18 ,  H04W4/80 ,  H04W88/02 ,  G06K7/10

Abstract: A near-field communication device operates to transmit data by near-field communications techniques to another device. The near-field communication device includes a memory that stores a message to be transmitted in an ASCII format. The message is retrieved from the memory and transmitted using the near-field communications techniques in an ASCII format.

公开(公告)号：US11615857B2

公开(公告)日：2023-03-28

申请号：US17224024

申请日：2021-04-06

Applicant: STMicroelectronics S.r.l. ,  STMicroelectronics (Rousset) SAS

Inventor： Francesco La Rosa ,  Enrico Castaldo ,  Francesca Grande ,  Santi Nunzio Antonino Pagano ,  Giuseppe Nastasi ,  Franco Italiano

IPC: G11C16/00 ,  G11C16/34 ,  G11C16/10 ,  G11C16/14 ,  G11C16/26 ,  H01L27/11529 ,  G11C16/04

Abstract: A semiconductor well of a non-volatile memory houses memory cells. The memory cells each have a floating gate and a control gate. Erasing of the memory cells includes biasing the semiconductor well with a first erase voltage having an absolute value greater than a breakdown voltage level of bipolar junctions of a control gate switching circuit of the memory. An absolute value of the first erase voltage is based on a comparison of a value of an indication of wear of the memory cells to a wear threshold value.

公开(公告)号：US11601310B2

公开(公告)日：2023-03-07

申请号：US17580000

申请日：2022-01-20

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Yoann Bouvet

IPC: H04L27/233 ,  H04L27/26 ,  H04L27/00

Abstract: In accordance with an embodiment, a device configured to detect a presence of at least one digital pattern within a signal includes J memory circuits having respectively Nj memory locations; and processing circuitry comprising an accumulator configured to successively address the memory locations of the J memory circuits in a circular manner at frequency F and during an acquisition time, and successively accumulate and store values indicative of a signal intensity in parallel in the J addressed memory locations of the J memory circuits, and a detector configured to detect the possible presence of the at least one pattern.

公开(公告)号：US20230064471A1

公开(公告)日：2023-03-02

申请号：US17885086

申请日：2022-08-10

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Laurent LOPEZ

IPC: H03K17/16

Abstract: A power switch device includes a first terminal intended to be connected to a source of a first supply potential, a second terminal configured to supply a second potential, and a third terminal intended to be connected to a second source of a third supply potential. The device includes a first PMOS transistor having a source connected to the second terminal and a drain connected to the third terminal, a second PMOS transistor having a source connected to the second terminal, and a third PMOS transistor having a source connected to the first terminal and a drain connected to the drain of the second transistor. A control circuit generates gate control signals to control operation of the first, second and third PMOS transistors dependent on the first, second, and third supply potentials.

公开(公告)号：US20230058758A1

公开(公告)日：2023-02-23

申请号：US17884245

申请日：2022-08-09

Applicant: STMICROELECTRONICS (ROUSSET) SAS ,  STMICROELECTRONICS (ALPS) SAS

Inventor： Alexandre TRAMONI ,  Patrick ARNOULD

IPC: G06F1/26

Abstract: The present disclosure relates to a method for powering an electronic device. The electronic device includes at least one universal integrated circuit card or at least one secure element; at least one power supply circuit for said card or secure element; and at least one near field communication module. When the near field communication module changes from a standby or inactive state to an active state, the following successive operations are performed: —the components and circuits of said electronic device are started; —programs of the electronic device and said secure card or element are started at the same time.

公开(公告)号：US20230055356A1

公开(公告)日：2023-02-23

申请号：US17884238

申请日：2022-08-09

Applicant: STMICROELECTRONICS (ROUSSET) SAS ,  STMICROELECTRONICS (ALPS) SAS

Inventor： Alexandre TRAMONI ,  Patrick ARNOULD

IPC: G06K19/07

Abstract: The present disclosure relates to an electronic device comprising: at least one universal integrated circuit card or at least one secure element and at least one power supply circuit for said card or secure element, said power supply circuit being connected to at least a first power supply voltage source of the electronic device and comprising a voltage detector adapted to determine whether said first voltage source provides a first power supply voltage different from a reference voltage; and at least one near field communication module adapted to enter an active mode whenever said voltage detector determines that said first supply voltage is different from the reference voltage.