公开(公告)号：US20210003770A1

公开(公告)日：2021-01-07

申请号：US17026819

申请日：2020-09-21

Applicant: STMicroelectronics SA

Inventor： Folly Eli Ayi-Yovo ,  Cédric Durand ,  Frédéric Gianesello

IPC: F21V8/00 ,  G02B6/36 ,  G02B6/02 ,  G02B6/30 ,  B23K26/00 ,  B23K26/364 ,  B23K26/402 ,  B23K26/0622 ,  G02B6/12

Abstract: An embodiment optical device includes a glass plate, a first trench disposed in the glass plate, and a second trench disposed in the glass plate. The second trench crosses the first trench, and the first trench has an open end in a first wall of the second trench. The optical device includes a waveguide disposed inside the first trench, where the waveguide is formed of a material having a refractive index different from that of the glass plate, and a mirror on a second wall of the second trench opposite the first wall and waveguide. The optical device includes an encapsulation layer filling the second trench and covering all of an upper surface of the waveguide and having a refractive index that is different from the waveguide and the glass plate.

公开(公告)号：US20200379178A1

公开(公告)日：2020-12-03

申请号：US16889164

申请日：2020-06-01

Applicant: STMicroelectronics SA

Inventor： Frederic GIANESELLO ,  Ophelie FOISSEY ,  Cedric DURAND

IPC: G02B6/27 ,  G02B6/34

Abstract: An integrated optoelectronic or optical device is formed by a polarization-splitting grating coupler including two optical waveguides, a common optical coupler and flared optical transitions between the optical coupler and the optical waveguides. The optical coupler is configured for supporting input/output of optical waves. A first region of the optical coupler lies at a distance from the flared optical transitions. The first region includes a first recessed pattern. Second regions of the optical coupler lie between the first region and the flared optical transitions, respectively, in an adjoining relationship. The second regions include a second recessed pattern different from the first recessed pattern.

公开(公告)号：US10782468B2

公开(公告)日：2020-09-22

申请号：US15730415

申请日：2017-10-11

Applicant: STMicroelectronics SA

Inventor： Folly Eli Ayi-Yovo ,  Cédric Durand ,  Frédéric Gianesello

IPC: F21V8/00 ,  G02B6/02 ,  G02B6/36 ,  G02B6/30 ,  B23K26/00 ,  B23K26/364 ,  B23K26/402 ,  B23K26/0622 ,  G02B6/12 ,  B23K103/00

Abstract: The present invention relates to a method for manufacturing an optical device comprising forming a first trench in a glass plate and a second trench perpendicular to the first trench, wherein the first trench has an end opening into the second trench. The trenches are treated with hydrofluoric acid. The first trench is filled with a material to form a waveguide, and a mirror is formed on the wall of the second trench opposite the waveguide. An encapsulation layer is deposited over the glass plate, waveguide and second trench.

公开(公告)号：US20200252059A1

公开(公告)日：2020-08-06

申请号：US16747341

申请日：2020-01-20

Applicant: STMicroelectronics (Crolles 2) SAS ,  STMicroelectronics SA

Inventor： Capucine LECAT-MATHIEU DE BOISSAC ,  Fady ABOUZEID ,  Gilles GASIOT ,  Philippe ROCHE ,  Victor MALHERBE

IPC: H03K5/14 ,  H03K5/135

Abstract: A first circuit includes a first chain of identical stages defining first and second delay lines. A second circuit includes a second chain of identical stages defining third and fourth delay lines. The stages of the second chain are identical to the stages of the first chain. A third circuit selectively couples one of the third delay line, the fourth delay line, or a first input of the third circuit to an input of the first circuit.

公开(公告)号：US10535552B2

公开(公告)日：2020-01-14

申请号：US15892696

申请日：2018-02-09

Applicant: STMicroelectronics SA

Inventor： Didier Dutartre ,  Herve Jaouen

IPC: H01L21/762 ,  H01L21/02

Abstract: A semiconductor wafer suitable for fabricating an SOI substrate is provided by: producing a first layer of polycrystalline semiconductor on a top side of a semiconductor carrier; then forming an interface zone on a top side of the first layer, wherein the interface zone has a structure different from a crystal structure of the first layer; and then producing a second layer of polycrystalline semiconductor on the interface zone.

公开(公告)号：US20200013901A1

公开(公告)日：2020-01-09

申请号：US16458363

申请日：2019-07-01

Applicant: STMicroelectronics SA

Inventor： Louise De Conti ,  Philippe Galy

IPC: H01L29/786 ,  H01L29/423 ,  H01L27/12

Abstract: An integrated electronic device, comprising at least one MOS transistor produced in and on an active zone of a silicon-on-insulator substrate, said at least one first transistor including a first gate region and a first substrate contact zone that is surrounded by the first gate region.

公开(公告)号：US10515946B2

公开(公告)日：2019-12-24

申请号：US15982443

申请日：2018-05-17

Applicant: STMicroelectronics SA

Inventor： Jean Jimenez ,  Boris Heitz ,  Johan Bourgeat ,  Agustin Monroy Aguirre

IPC: H01L27/02 ,  H01L27/12 ,  H01L27/102 ,  H01L29/74 ,  H01L29/87

Abstract: A semiconductor device includes a thyristor disposed in a semiconductor body. The thyristor has an anode, a cathode, a first bipolar transistor located on an anode side, and a second bipolar transistor located on a cathode side. The first and second bipolar transistors are nested and connected between the anode and the cathode. A MOS transistor is disposed in the semiconductor body. The MOS transistor is coupled between a collector region and an emitter region of the second bipolar transistor. The MOS transistor has a gate region connected to the cathode via a resistive semiconductor region that incorporates at least a part of a base region of the second bipolar transistor.

公开(公告)号：US10514749B2

公开(公告)日：2019-12-24

申请号：US15467614

申请日：2017-03-23

Applicant: STMicroelectronics (Crolles 2) SAS ,  STMicroelectronics (Alps) SAS ,  STMicroelectronics SA

Inventor： Vincent Huard ,  Silvia Brini ,  Chittoor Parthasarathy

IPC: G06F1/26 ,  G06F1/32 ,  G06F1/3234 ,  G06F11/30 ,  G06F11/32 ,  G06F15/78 ,  G06F1/3206 ,  G06F1/324 ,  G06F1/3296

Abstract: A system on a chip includes at least one integrated circuit that is configured to operate at least at one operating point. A monitoring circuit acquires at least the cumulative duration of activity of the at least one integrated circuit. An evaluation circuit establish at least one instantaneous state of aging of the at least one integrated circuit based on the at least one cumulative duration of activity. An adjustment circuit operates to change the at least one operating point on the basis of the at least one state of aging of the at least one integrated circuit.

公开(公告)号：US10511147B2

公开(公告)日：2019-12-17

申请号：US15992573

申请日：2018-05-30

Applicant: Commissariat A L'Energie Atomique et aux Energies Alternatives ,  STMICROELECTRONICS SA ,  STMICROELECTRONICS (CROLLES 2) SAS

Inventor： Thomas Ferrotti ,  Badhise Ben Bakir ,  Alain Chantre ,  Sebastien Cremer ,  Helene Duprez

IPC: H01S5/125 ,  H01S5/12 ,  H01S5/02 ,  H01S5/026 ,  H01S5/10 ,  H01S5/343 ,  H01S5/022 ,  H01S5/042 ,  H01S5/187 ,  H01S5/323 ,  G02B6/12 ,  G02B6/30 ,  G02B6/34

Abstract: The invention relates to a III-V heterostructure laser device (1) arranged in and/or on silicon, comprising: a III-V heterostructure gain medium (3); and an optical rib waveguide (11), arranged facing the gain medium (3) and comprising a slab waveguide (15) equipped with a longitudinal rib (17), the optical rib waveguide (11) being arranged in the silicon. The optical rib waveguide (11) is oriented so that at least one Bragg grating (19, 19a, 19b) is arranged on that side (21) of the slab waveguide (15) which is proximal relative to the gain medium (3) and in that the rib (17) is placed on that side (23) of the slab waveguide (15) that is distal relative to the gain medium (3).

公开(公告)号：US20190319453A1

公开(公告)日：2019-10-17

申请号：US15951806

申请日：2018-04-12

Applicant: STMicroelectronics International N.V. ,  STMicroelectronics SA

Inventor： Radhakrishnan SITHANANDAM ,  Divya AGARWAL ,  Ghislain TROUSSIER ,  Jean JIMENEZ ,  Malathi KAR

IPC: H02H9/04 ,  H01L27/02

Abstract: Electrostatic discharge (ESD) protection is provided in using a supply clamp circuit using an ESD event actuated MOSFET device. Triggering of the MOSFET device is made at both the gate terminal and the substrate (back gate) terminal. Additionally, the MOSFET device can be formed of cascoded MOSFETs.