PIEZOELECTRIC MICROMACHINED ULTRASONIC TRANSDUCER

    公开(公告)号:US20210276044A1

    公开(公告)日:2021-09-09

    申请号:US17191475

    申请日:2021-03-03

    Abstract: A method for manufacturing a PMUT device including a piezoelectric element located at a membrane element is provided. The method includes receiving a silicon on insulator substrate having a first silicon layer, an oxide layer, and a second silicon layer. Portions of a first surface of the second silicon layer are exposed by removing exposed side portions of the first silicon layer and corresponding portions of the oxide layer, and a central portion including the remaining portions of the first silicon layer and of the oxide layer is defined. Anchor portions for the membrane element are formed at the exposed portions of the first surface of the second silicon layer. The piezoelectric element is formed above the central portion, and the membrane element is defined by selectively removing the second layer and removing the remaining portion of the oxide from under the remaining portion of the first silicon layer.

    Electronic device for performing step counting with false-positive rejection

    公开(公告)号:US11112268B2

    公开(公告)日:2021-09-07

    申请号:US15688152

    申请日:2017-08-28

    Abstract: Disclosed herein is a method including receiving multi-axis accelerometer data representing a potential step taken by a user of an electronic device. The method also includes determining whether the potential step represented by the multi-axis accelerometer data is a false. This determination is made by calculating statistical data from the multi-axis accelerometer data, and applying a decision tree to the statistical data to perform a cross correlation that determines whether the potential step is a false positive. If the potential step is not a false positive, a step detection process is performed to determine whether the potential step is a countable step and, if the potential step is found to be a countable step, a step counter is incremented.

    Photonic Wafer Level Testing Systems, Devices, and Methods of Operation

    公开(公告)号:US20210270699A1

    公开(公告)日:2021-09-02

    申请号:US17318831

    申请日:2021-05-12

    Abstract: A method of testing a photonic device includes providing a plurality of optical test signals at respective inputs of a first plurality of inputs of an optical input circuit located on a substrate, combining the plurality of optical test signals into a combined optical test signal at an output of the optical input circuit, transmitting the combined optical test signal through the output to an input waveguide of an optical device under test, the optical device under test being located on the substrate, and measuring a response of the optical device under test to the combined optical test signal. Each of the plurality of optical test signals comprises a respective dominant wavelength of a plurality of dominant wavelengths.

    Inverter and method for measuring phase currents in an electric machine

    公开(公告)号:US11105836B2

    公开(公告)日:2021-08-31

    申请号:US16746444

    申请日:2020-01-17

    Abstract: A three-phase load is powered by a PWM (e.g., SVPWM) driven DC-AC inverter having a single shunt-topology. A shunt voltage and a branch voltage of the inverter (across a transistor to be calibrated) are measured during a second period of each SVPWM sector, and the drain-to-source resistance of the calibrated transistor is calculated. During the fourth period of each SVPWM sector, the branch voltage is measured again, and another branch voltage across another transistor is measured. Using the drain-to-source resistance of the calibrated transistor and the voltage across the calibrated transistor measured during the fourth period, the phase current through the calibrated transistor is calculated. Using the other branch voltage measured during the fourth period and the drain-to-source resistance of its corresponding transistor (known from a prior SVPWM sector), the phase current through that transistor is calculated. From the two calculated phase currents, the other phase current can be calculated.

    MEMS INCLINOMETER HAVING A REDUCED VIBRATION RECTIFICATION ERROR

    公开(公告)号:US20210261403A1

    公开(公告)日:2021-08-26

    申请号:US17179157

    申请日:2021-02-18

    Abstract: A MEMS inclinometer includes a substrate, a first mobile mass and a sensing unit. The sensing unit includes a second mobile mass, a number of elastic elements, which are interposed between the second mobile mass and the substrate and are compliant in a direction parallel to a first axis, and a number of elastic structures, each of which is interposed between the first and second mobile masses and is compliant in a direction parallel to the first axis and to a second axis. The sensing unit further includes a fixed electrode that is fixed with respect to the substrate and a mobile electrode fixed with respect to the second mobile mass, which form a variable capacitor.

    ANALYSIS METHOD OF A DEVICE, PERFORMED THROUGH A MEMS SENSOR, AND SYSTEM THEREOF INCLUDING THE DEVICE AND THE MEMS SENSOR

    公开(公告)号:US20210253419A1

    公开(公告)日:2021-08-19

    申请号:US17175410

    申请日:2021-02-12

    Abstract: An analysis method of a device through a MEMS sensor is provided in which the MEMS sensor includes a control unit and a sensing assembly coupled to the device. The analysis method includes acquiring, through the sensing assembly, first data indicative of an operative state of the device. Testing is performed for the presence of a first abnormal operating condition of the device. If the first abnormal operating condition of the device is confirmed, a self-test of the sensing assembly is performed to generate a quantity indicative of an operative state of the sensing assembly. The self-test includes acquiring, through the sensing assembly, second data indicative of the operative state of the sensing assembly, generating a signature according to the second data, and processing the signature through deep learning techniques to generate said quantity.

    Anti-aging architecture for power MOSFET device

    公开(公告)号:US11094807B2

    公开(公告)日:2021-08-17

    申请号:US16561670

    申请日:2019-09-05

    Abstract: A power MOS stage includes a first power MOS device and a second power MOS devices connected in parallel between a first node and a second node, the first power MOS device having a first voltage rating and the second power MOS device having a second voltage rating that is lower than the first voltage rating. A driver circuit is configured to drive control nodes of the first and second power MOS devices in a sequential manner when actuating the power MOS stage by actuating the first power MOS device before actuating the second power MOS device. The control nodes of the first and second power MOS devices are further driven in a sequential manner when deactuating the power MOS stage by deactuating the second power MOS device before deactuating the first power MOS device.

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