Electronic apparatus and BIOS updating apparatus thereof
    31.
    发明授权
    Electronic apparatus and BIOS updating apparatus thereof 有权
    电子设备及其BIOS更新装置

    公开(公告)号:US09311075B2

    公开(公告)日:2016-04-12

    申请号:US13671569

    申请日:2012-11-08

    CPC classification number: G06F8/656

    Abstract: An electronic apparatus including a central processing unit (CPU), a chipset, a first interface circuit, a temporary memory, a BIOS (basic input/output system) memory, a second interface circuit and a first switcher is provided. The chipset is coupled to the CPU and the first switcher. The temporary memory is coupled to the first switcher and the first interface circuit. The first interface circuit is coupled to the electronic apparatus and an extended storage including a first BIOS. The second interface circuit is coupled to the first switcher and the BIOS memory. If the first BIOS is stored in the temporary memory, the temporary memory is coupled to the chipset by the first switcher; if the first BIOS is not stored in the temporary memory, the second interface circuit is coupled to the chipset by the first switcher. The electronic device can safely updates the BIOS.

    Abstract translation: 提供了包括中央处理单元(CPU),芯片组,第一接口电路,临时存储器,BIOS(基本输入/输出系统)存储器,第二接口电路和第一切换器的电子设备。 该芯片组耦合到CPU和第一个切换台。 临时存储器耦合到第一切换器和第一接口电路。 第一接口电路耦合到电子设备和包括第一BIOS的扩展存储器。 第二接口电路耦合到第一切换器和BIOS存储器。 如果第一BIOS存储在临时存储器中,则临时存储器通过第一切换器耦合到芯片组; 如果第一BIOS不存储在临时存储器中,则第二接口电路通过第一切换器耦合到芯片组。 电子设备可以安全地更新BIOS。

    Method for adaptively driving data transmission and communication device using the same
    32.
    发明授权
    Method for adaptively driving data transmission and communication device using the same 有权
    用于自适应地驱动数据传输和通信设备的方法

    公开(公告)号:US08848826B2

    公开(公告)日:2014-09-30

    申请号:US13470365

    申请日:2012-05-14

    CPC classification number: H04B1/44 H04L25/0264 H04L25/03885

    Abstract: A method for adaptively driving data transmission and a communication device using the same are provided. The proposed method includes following procedures. Detection result is generated after detecting a receiving signal on a receiving path of the communication device. Driving parameter is generated according to the detection result. Finally, a transmitting signal on a transmitting path is adjusted according to the driving parameter.

    Abstract translation: 提供一种用于自适应地驱动数据传输的方法和使用该方法的通信装置。 所提出的方法包括以下步骤。 在检测到通信装置的接收路径上的接收信号之后产生检测结果。 根据检测结果生成驱动参数。 最后,根据驱动参数调整发送路径上的发送信号。

    Reference current generation circuit
    33.
    发明授权
    Reference current generation circuit 有权
    参考电流发生电路

    公开(公告)号:US08829881B2

    公开(公告)日:2014-09-09

    申请号:US13585797

    申请日:2012-08-14

    Applicant: Yu-Chuan Lin

    Inventor: Yu-Chuan Lin

    CPC classification number: G05F1/561

    Abstract: A reference current generation circuit is provided, in which a current generated according to a bandgap voltage is not directly used as a reference current, but the current generated according to the bandgap voltage is used to adjust an output reference current. In this way, the reference voltage is generated without using an external resistor, so as to effectively decrease the production cost.

    Abstract translation: 提供了一种参考电流产生电路,其中根据带隙电压产生的电流不直接用作参考电流,而是根据带隙电压产生的电流用于调整输出参考电流。 以这种方式,在不使用外部电阻的情况下产生参考电压,从而有效降低生产成本。

    ENCRYPTION AND DECRYPTION DEVICE FOR PORTABLE STORAGE DEVICE AND ENCRYPTION AND DECRYPTION METHOD THEREOF
    34.
    发明申请
    ENCRYPTION AND DECRYPTION DEVICE FOR PORTABLE STORAGE DEVICE AND ENCRYPTION AND DECRYPTION METHOD THEREOF 有权
    便携式存储设备的加密和分解设备及其加密和分解方法

    公开(公告)号:US20140208125A1

    公开(公告)日:2014-07-24

    申请号:US14154194

    申请日:2014-01-14

    CPC classification number: G06F21/85 G06F21/78 G06F2221/2107

    Abstract: An encryption and decryption device for a portable storage device and an encryption and decryption method thereof are provided. The encryption and decryption device includes a storage element, a control element and an encryption and decryption circuit. The control element receives a password, saves the password to the storage element and provides an encryption and decryption command. The encryption and decryption circuit is electrically connected to a portable storage device, receives the encryption and decryption command, reads the password stored in the storage element according to the encryption and decryption command, and encrypts or decrypts data stored in the portable storage device by utilizing the password according to whether the data have been encrypted. After the data are encrypted or decrypted, the encryption and decryption circuit clears the password in the storage element.

    Abstract translation: 提供了一种用于便携式存储设备的加密和解密设备及其加密和解密方法。 加密和解密装置包括存储元件,控制元件和加密和解密电路。 控制元件接收密码,将密码保存到存储元件,并提供加密和解密命令。 加密和解密电路电连接到便携式存储装置,接收加密和解密命令,根据加密和解密命令读取存储在存储元件中的密码,并利用存储在便携式存储装置中的数据进行加密或解密 密码根据数据是否被加密。 在数据被加密或解密之后,加密和解密电路清除存储元件中的密码。

    Clock generating device, method thereof and computer system using the same
    35.
    发明授权
    Clock generating device, method thereof and computer system using the same 有权
    时钟发生装置及其使用方法和计算机系统

    公开(公告)号:US08266470B2

    公开(公告)日:2012-09-11

    申请号:US12564907

    申请日:2009-09-22

    Abstract: A clock generating device, method thereof and a computer system using the same are provided. The clock generating device includes a PLL module and a tuning module. The PLL module receives a reference clock signal, and generates an output clock signal as a basic clock of a computer system according to a phase difference between a reference clock signal and a feedback signal. The PLL module includes a frequency divider adjusting an intrinsic frequency dividing ratio according to a control signal and performs a frequency dividing processing on the output clock signal to generate a feedback signal. The tuning module coupled with the PLL module generates the control signal according to a VID of a CPU and one of the feedback signal and the reference clock. Therefore, the operation frequency of the components serving the output clock signal as the basic frequency in the computer system can be synchronously tuned.

    Abstract translation: 提供了一种时钟发生装置及其方法以及使用其的计算机系统。 时钟发生装置包括PLL模块和调谐模块。 PLL模块接收参考时钟信号,并根据参考时钟信号和反馈信号之间的相位差产生输出时钟信号作为计算机系统的基本时钟。 PLL模块包括根据控制信号调整固有分频比的分频器,并对输出时钟信号进行分频处理以产生反馈信号。 与PLL模块耦合的调谐模块根据CPU的VID和反馈信号和参考时钟之一产生控制信号。 因此,可以同步调整作为计算机系统中的基本频率的输出时钟信号的组件的操作频率。

    SYSTEM AND METHOD OF INTEGRATING DATA ACCESSING COMMANDS
    36.
    发明申请
    SYSTEM AND METHOD OF INTEGRATING DATA ACCESSING COMMANDS 审中-公开
    集成数据访问命令的系统和方法

    公开(公告)号:US20090172264A1

    公开(公告)日:2009-07-02

    申请号:US12238152

    申请日:2008-09-25

    CPC classification number: G06F3/0659 G06F3/061 G06F3/0679 G06F12/0246

    Abstract: A data accessing command integration method includes the following steps. Firstly, M data accessing commands are sequentially received through a bus, wherein N data accessing commands contained in the M data accessing commands have the same command type and comply with a sequential address relationship. Next, the N data accessing commands are re-ordered according to the addressing sequence, so that a first data corresponding to the re-ordered N data accessing commands are sequentially accessed in the data memory.

    Abstract translation: 数据访问命令集成方法包括以下步骤。 首先,通过总线顺序地接收M个数据访问命令,其中包含在M个数据访问命令中的N个数据访问命令具有相同的命令类型并且遵循顺序地址关系。 接下来,根据寻址序列重新排序N个数据访问命令,从而在数据存储器中顺序地访问对应于重新排序的N个数据访问命令的第一数据。

    Color image enhancement apparatus and method
    37.
    发明申请
    Color image enhancement apparatus and method 审中-公开
    彩色图像增强装置及方法

    公开(公告)号:US20060274378A1

    公开(公告)日:2006-12-07

    申请号:US11446113

    申请日:2006-06-05

    CPC classification number: H04N1/608

    Abstract: A color image enhancement apparatus has a color attribute interpreter and a color attribute adjuster. The color attribute interpreter generates an adjust signal according to a Hue, a Saturation and a Brightness of a pixel data. Of the adjust signal, each adjustment for each of the Hue, the Saturation and the Brightness is determined by all of the Hue, the Saturation and the Brightness of the pixel data. The color attribute adjuster is connected to the color attribute interpreter. The color attribute adjuster receives the adjust signal and adjusts the transformed color attribute according to the adjust signal.

    Abstract translation: 彩色图像增强装置具有颜色属性解释器和颜色属性调整器。 颜色属性解释器根据像素数据的色相,饱和度和亮度生成调整信号。 在调整信号中,每个色调,饱和度和亮度的每个调整由像素数据的所有色相,饱和度和亮度决定。 颜色属性调整器连接到颜色属性解释器。 颜色属性调整器接收调整信号,并根据调整信号调整变换后的颜色属性。

    Apparatus and method for compensating regional nonuniformity of a display panel
    38.
    发明申请
    Apparatus and method for compensating regional nonuniformity of a display panel 审中-公开
    用于补偿显示面板的区域不均匀性的装置和方法

    公开(公告)号:US20060187182A1

    公开(公告)日:2006-08-24

    申请号:US11355101

    申请日:2006-02-16

    CPC classification number: G09G5/10 G09G2320/0233 G09G2320/0285 G09G2360/147

    Abstract: Several display regions are defined on a display panel, and each display region has its panel characteristic data. A pixel data is received and the determined display region of the pixel data is determined. The pixel data is calibrated according to the panel characteristic data of the determined display region, and then the calibrated pixel data is transmitted to the display panel.

    Abstract translation: 在显示面板上定义几个显示区域,每个显示区域具有面板特征数据。 接收像素数据,确定确定的像素数据的显示区域。 根据所确定的显示区域的面板特性数据对像素数据进行校准,然后校准的像素数据被发送到显示面板。

    Testing circuit for testing universal serial bus

    公开(公告)号:US12181536B2

    公开(公告)日:2024-12-31

    申请号:US18178514

    申请日:2023-03-05

    Abstract: A testing circuit for testing a universal serial bus (USB) of an electronic device includes a controller, a first switch, a pull-down resistor, a gating pull-up resistor, and a second switch. The controller provides a control signal according to a power receiving condition of the electronic device. A control terminal of the first switch is coupled to the controller. The pull-down resistor is coupled between a configuration channel pin of the USB and a first terminal of the first switch. The gating pull-up resistor is coupled between the configuration channel pin and the control terminal of the first switch. A control terminal of the second switch is coupled to the controller. A first terminal of the second switch is coupled to a second terminal of the first switch and a ground pin of the USB. A second terminal of the second switch is coupled to a reference low voltage.

    TESTING CIRCUIT FOR TESTING UNIVERSAL SERIAL BUS

    公开(公告)号:US20240248151A1

    公开(公告)日:2024-07-25

    申请号:US18178514

    申请日:2023-03-05

    CPC classification number: G01R31/66

    Abstract: A testing circuit for testing a universal serial bus (USB) of an electronic device includes a controller, a first switch, a pull-down resistor, a gating pull-up resistor, and a second switch. The controller provides a control signal according to a power receiving condition of the electronic device. A control terminal of the first switch is coupled to the controller. The pull-down resistor is coupled between a configuration channel pin of the USB and a first terminal of the first switch. The gating pull-up resistor is coupled between the configuration channel pin and the control terminal of the first switch. A control terminal of the second switch is coupled to the controller. A first terminal of the second switch is coupled to a second terminal of the first switch and a ground pin of the USB. A second terminal of the second switch is coupled to a reference low voltage.

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