公开(公告)号：US11494430B2

公开(公告)日：2022-11-08

申请号：US16441032

申请日：2019-06-14

Applicant: ASMedia Technology Inc.

Inventor： Wei-Kan Hwang

IPC: G06F9/00 ,  G06F16/58 ,  G06N3/08 ,  G06F9/46 ,  G06K9/62 ,  G06F16/53

Abstract: A data storage apparatus and a data prediction method thereof are provided. The data storage apparatus includes a memory unit and a prediction unit. The prediction unit acquires a plurality of access location data of a plurality of data access actions of a prior access history of the memory unit. The prediction unit analyzes the prior access history of the memory unit. The prediction unit performs a quantification process on the access location data to acquire a plurality of quantized data corresponding to the prior access history. The prediction unit predicts a data pre-accessing target of the memory unit according to the quantized data.

公开(公告)号：US10417164B2

公开(公告)日：2019-09-17

申请号：US15848553

申请日：2017-12-20

Applicant: ASMedia Technology Inc.

Inventor： Chin-Lung Wu ,  Wei-Yun Chang

IPC: G06F13/42 ,  G06F13/28 ,  G06F13/38 ,  G06F13/40

Abstract: A synchronous transmission device includes a first communication port, a first bus instance and a second bus instance. The first communication port is connected to the first endpoint and the second endpoint. The first bus instance executes a first data transmission with the first endpoint according to a first node of a first schedule list. The first node corresponds to the first endpoint, and the first bus instance corresponds to the first communication port. When the first data transmission is executed, the first bus instance is further configured to determine whether the second bus instance is idle. When the second bus instance is idle, the first bus instance controls the second bus instance to execute a second data transmission with the second endpoint according to a second node of the first schedule list. The second node of the first schedule list corresponds to the second endpoint.

公开(公告)号：US20190108151A1

公开(公告)日：2019-04-11

申请号：US16027280

申请日：2018-07-04

Applicant: ASMedia Technology Inc.

Inventor： Kuo-Lung LI

IPC: G06F13/28 ,  G06F13/40 ,  G06F13/16 ,  G06F13/42

CPC classification number: G06F13/28 ,  G06F13/1642 ,  G06F13/1673 ,  G06F13/4027 ,  G06F13/4282

Abstract: A bridge device includes a first physical layer circuit, a first buffer memory, a DMA controller, and a processor. The first physical layer circuit is configured to connect to an upstream device. The first buffer memory is configured to store a first data and transfer data to the upstream device via the first physical layer circuit. The DMA controller is coupled to the first buffer memory and configured to access the first data in the first buffer memory to read and/or write a storage device correspondingly. The processor is coupled to the first buffer memory and the DMA controller. When the bridge device receives a clear feature command from the upstream device, the processor is configured to reset the first buffer memory and the DMA controller to stop the data transferring between the upstream device and the bridge device.

公开(公告)号：US10198395B2

公开(公告)日：2019-02-05

申请号：US15643495

申请日：2017-07-07

Applicant: ASMedia Technology Inc.

Inventor： Wei-Kan Hwang

IPC: G06F13/36 ,  G06F13/42

Abstract: A port multiplier system is provided. The port multiplier system comprises a first port multiplier and a second port multiplier. The first port multiplier is configured to receive a plurality of first frame information structures from a host. Each of the first frame information structure corresponds to a first port multiplier port number. The first port multiplier sends the first frame information structures that correspond to the first port multiplier port numbers, respectively, to a first downstream port of the first port multiplier according to first port multiplier port number. The second port multiplier is configured to send the first frame information structures that are sent to the first downstream port to a plurality of second downstream ports of the second port multiplier, respectively. An operation method is also provided.

公开(公告)号：US09465556B2

公开(公告)日：2016-10-11

申请号：US14273528

申请日：2014-05-08

Applicant: ASMedia Technology Inc.

Inventor： Ming-Hui Chiu ,  Chia-Hsin Chen ,  Yung-Chi Hwang

IPC: G06F13/00 ,  G06F3/06 ,  G06F11/00

CPC classification number: G06F3/0659 ,  G06F3/0604 ,  G06F3/061 ,  G06F3/0689 ,  G06F11/00 ,  G06F2003/0692 ,  G06F2212/262

Abstract: A disk array system and a data processing method are provided. The data processing method is applied to the disk array system. The disk array system is a redundancy array of independent disk 0 (RAID 0) system. The disk array system includes a plurality of disks. The data processing method includes: receiving a reading command; determining whether to divide the reading command to a plurality of reading command segments according to the reading command; and assigning the reading command to a corresponding disk of the disks to read data stored in the corresponding disk accordingly when it is determined that the reading command is not divided.

Abstract translation: 提供了磁盘阵列系统和数据处理方法。 数据处理方法应用于磁盘阵列系统。 磁盘阵列系统是独立磁盘0（RAID 0）系统的冗余阵列。 磁盘阵列系统包括多个磁盘。 数据处理方法包括：接收读取命令; 根据读取命令确定是否将读取命令划分为多个读取命令段; 以及当确定所述读取命令未被划分时，将所述读取命令分配给所述盘的相应盘以相应地读取存储在所述对应盘中的数据。

公开(公告)号：US09459811B2

公开(公告)日：2016-10-04

申请号：US14273539

申请日：2014-05-08

Applicant: ASMedia Technology Inc.

Inventor： Ming-Hui Chiu ,  Chia-Hsin Chen ,  Yung-Chi Hwang ,  Ching-Fa Hsiao

IPC: G06F3/06

CPC classification number: G06F3/0659 ,  G06F3/0613 ,  G06F3/0617 ,  G06F3/065 ,  G06F3/0689 ,  G06F2003/0692

Abstract: A disk array system and a data processing method are provided. The data processing method is applied to the disk array system. The disk array system includes a first disk and a second disk. The data processing method includes: receiving a reading command, wherein the reading, command includes a data starting address; determining to assign the reading command to the first disk or the second disk according to the data starting address of the reading command and a stripe size; and reading corresponding data according to the reading command from the first disk or the second disk which receives the reading command.

Abstract translation: 提供了磁盘阵列系统和数据处理方法。 数据处理方法应用于磁盘阵列系统。 磁盘阵列系统包括第一磁盘和第二磁盘。 数据处理方法包括：接收读取命令，其中读取命令包括数据起始地址; 确定根据读取命令的数据起始地址和条带大小将读取命令分配给第一盘或第二盘; 以及根据从接收到读取命令的第一盘或第二盘读取命令读取相应数据。

公开(公告)号：US09330038B2

公开(公告)日：2016-05-03

申请号：US14106869

申请日：2013-12-16

Applicant: ASMedia Technology Inc.

Inventor： Yang-Chen Liu ,  Hui-Yu Tang ,  Li-Feng Kuo

IPC: G06F13/00 ,  G06F13/362 ,  G06F13/38 ,  G06F13/40

CPC classification number: G06F13/3625 ,  G06F13/385 ,  G06F13/4022

Abstract: The bandwidth allocation apparatus includes a high bandwidth arbitration module, a low bandwidth arbitration module and a multiplexer. The high bandwidth arbitration module is used to select one downstream device from the high bandwidth downstream device group for allowing uplink. The low bandwidth arbitration module is used to select one downstream device from the low bandwidth downstream device group for allowing uplink. The multiplexer selects the one of the access requests from the high bandwidth arbitration module or the low bandwidth arbitration module for allowing to uplink the access request to an upstream device. The access transmission times of the high bandwidth arbitration module and the low bandwidth arbitration module are counted respectively by a counting circuit.

Abstract translation: 带宽分配装置包括高带宽仲裁模块，低带宽仲裁模块和多路复用器。 高带宽仲裁模块用于从高带宽下游设备组中选择一个下行设备，以允许上行链路。 低带宽仲裁模块用于从低带宽下游设备组中选择一个下行设备，以允许上行链路。 多路复用器选择来自高带宽仲裁模块或低带宽仲裁模块的访问请求中的一个，以允许向上游设备上行接入请求。 高带宽仲裁模块和低带宽仲裁模块的接入传输时间分别由计数电路计数。

公开(公告)号：US20140208125A1

公开(公告)日：2014-07-24

申请号：US14154194

申请日：2014-01-14

Applicant: ASMedia Technology Inc.

Inventor： Kuo-Chi CHANG ,  Hsin-Hsiung WANG

IPC: G06F21/60

CPC classification number: G06F21/85 ,  G06F21/78 ,  G06F2221/2107

Abstract: An encryption and decryption device for a portable storage device and an encryption and decryption method thereof are provided. The encryption and decryption device includes a storage element, a control element and an encryption and decryption circuit. The control element receives a password, saves the password to the storage element and provides an encryption and decryption command. The encryption and decryption circuit is electrically connected to a portable storage device, receives the encryption and decryption command, reads the password stored in the storage element according to the encryption and decryption command, and encrypts or decrypts data stored in the portable storage device by utilizing the password according to whether the data have been encrypted. After the data are encrypted or decrypted, the encryption and decryption circuit clears the password in the storage element.

Abstract translation: 提供了一种用于便携式存储设备的加密和解密设备及其加密和解密方法。 加密和解密装置包括存储元件，控制元件和加密和解密电路。 控制元件接收密码，将密码保存到存储元件，并提供加密和解密命令。 加密和解密电路电连接到便携式存储装置，接收加密和解密命令，根据加密和解密命令读取存储在存储元件中的密码，并利用存储在便携式存储装置中的数据进行加密或解密 密码根据数据是否被加密。 在数据被加密或解密之后，加密和解密电路清除存储元件中的密码。

公开(公告)号：US20190227943A1

公开(公告)日：2019-07-25

申请号：US16038203

申请日：2018-07-18

Applicant: ASMedia Technology Inc.

Inventor： Wen-Cheng CHEN

IPC: G06F12/1009

Abstract: A method for accessing a physical region page (PRP) list includes obtaining a PRP address of a PRP list, in which the PRP address has M bits; performing operation to the first N bits of the PRP address and the N+1 th to Mth bits of the PRP address respectively to obtain a page base address if the PRP address is within a page boundary; and performing operation to the first N bits of the PRP address and the N+1 th to Mth bits of the PRP address respectively to obtain next PRP address pointer if the PRP address reaches the page boundary. N is an integer, and M is an integer larger than N.

公开(公告)号：US10114656B2

公开(公告)日：2018-10-30

申请号：US15470913

申请日：2017-03-28

Applicant: ASMedia Technology Inc.

Inventor： Chin-Lung Wu

IPC: G06F9/24 ,  G06F15/177 ,  G06F9/4401 ,  G06F1/24 ,  G06F1/32

Abstract: An electronic device comprising a mainboard and a device is provided. The mainboard includes a first storage circuit, a CPU circuit and a data transmission interface circuit. The first storage circuit is configured to store a first firmware code of a basic input/output system, the CPU circuit is coupled to the first storage circuit, the CPU circuit is configured to execute the first firmware code to run the basic input/output system, and the data transmission interface circuit is coupled to the CPU circuit. The device is coupled to the data transmission interface circuit of the mainboard for providing a device function to the CPU circuit via the data transmission interface circuit. The device includes a controller, the controller includes a second storage circuit, a microcontroller and a suspend power register. An operation method of the electronic device is also provided.