公开(公告)号：US08266470B2

公开(公告)日：2012-09-11

申请号：US12564907

申请日：2009-09-22

申请人： Ching-Yen Wu ,  Chi Chang

发明人： Ching-Yen Wu ,  Chi Chang

IPC分类号： G06F1/04 ,  G06F1/00

CPC分类号： G06F1/08 ,  G06F1/3203 ,  G06F1/324 ,  G06F1/3296 ,  Y02D10/126 ,  Y02D10/172

摘要： A clock generating device, method thereof and a computer system using the same are provided. The clock generating device includes a PLL module and a tuning module. The PLL module receives a reference clock signal, and generates an output clock signal as a basic clock of a computer system according to a phase difference between a reference clock signal and a feedback signal. The PLL module includes a frequency divider adjusting an intrinsic frequency dividing ratio according to a control signal and performs a frequency dividing processing on the output clock signal to generate a feedback signal. The tuning module coupled with the PLL module generates the control signal according to a VID of a CPU and one of the feedback signal and the reference clock. Therefore, the operation frequency of the components serving the output clock signal as the basic frequency in the computer system can be synchronously tuned.

摘要翻译： 提供了一种时钟发生装置及其方法以及使用其的计算机系统。 时钟发生装置包括PLL模块和调谐模块。 PLL模块接收参考时钟信号，并根据参考时钟信号和反馈信号之间的相位差产生输出时钟信号作为计算机系统的基本时钟。 PLL模块包括根据控制信号调整固有分频比的分频器，并对输出时钟信号进行分频处理以产生反馈信号。 与PLL模块耦合的调谐模块根据CPU的VID和反馈信号和参考时钟之一产生控制信号。 因此，可以同步调整作为计算机系统中的基本频率的输出时钟信号的组件的操作频率。

公开(公告)号：US20100077248A1

公开(公告)日：2010-03-25

申请号：US12564907

申请日：2009-09-22

申请人： Ching-Yen Wu ,  Chi Chang

发明人： Ching-Yen Wu ,  Chi Chang

IPC分类号： G06F1/04

CPC分类号： G06F1/08 ,  G06F1/3203 ,  G06F1/324 ,  G06F1/3296 ,  Y02D10/126 ,  Y02D10/172

摘要： A clock generating device, method thereof and a computer system using the same are provided. The clock generating device includes a PLL module and a tuning module. The PLL module receives a reference clock signal, and generates an output clock signal as a basic clock of a computer system according to a phase difference between a reference clock signal and a feedback signal. The PLL module includes a frequency divider adjusting an intrinsic frequency dividing ratio according to a control signal and performs a frequency dividing processing on the output clock signal to generate a feedback signal. The tuning module coupled with the PLL module generates the control signal according to a VID of a CPU and one of the feedback signal and the reference clock. Therefore, the operation frequency of the components serving the output clock signal as the basic frequency in the computer system can be synchronously tuned.

摘要翻译： 提供了一种时钟发生装置及其方法以及使用其的计算机系统。 时钟发生装置包括PLL模块和调谐模块。 PLL模块接收参考时钟信号，并根据参考时钟信号和反馈信号之间的相位差产生输出时钟信号作为计算机系统的基本时钟。 PLL模块包括根据控制信号调整固有分频比的分频器，并对输出时钟信号进行分频处理以产生反馈信号。 与PLL模块耦合的调谐模块根据CPU的VID和反馈信号和参考时钟之一产生控制信号。 因此，可以同步调整作为计算机系统中的基本频率的输出时钟信号的组件的操作频率。

公开(公告)号：US20070103242A1

公开(公告)日：2007-05-10

申请号：US11557109

申请日：2006-11-07

申请人： Ching-Yen Wu

发明人： Ching-Yen Wu

IPC分类号： H03K3/03

CPC分类号： H03K3/0322

摘要： A voltage controlled oscillator (VCO) with improved frequency characteristics is provided. The VCO includes a converting circuit supplied between a bias voltage and a ground voltage for converting the control voltage into a control current, a replica bias circuit coupled to the converting circuit for providing a swing voltage, and a ring oscillating circuit coupled to the replica bias circuit having at least two delay units coupled in series for successively delaying an input signal as the oscillating signal after a period of delay time.

摘要翻译： 提供了具有改进的频率特性的压控振荡器（VCO）。 VCO包括在偏置电压和接地电压之间提供的转换电路，用于将控制电压转换成控制电流，耦合到转换电路的复制偏置电路用于提供摆幅电压，以及耦合到复制偏置的环形振荡电路 电路具有串联耦合的至少两个延迟单元，用于在延迟时间段之后连续延迟输入信号作为振荡信号。

公开(公告)号：US20050084048A1

公开(公告)日：2005-04-21

申请号：US10710490

申请日：2004-07-15

申请人： Ching-Yen Wu

发明人： Ching-Yen Wu

IPC分类号： H03L7/081 ,  H03L7/091 ,  H04L7/00 ,  H04L7/033

CPC分类号： H04L7/0337 ,  H03L7/0814 ,  H03L7/091 ,  H04L7/0025

摘要： A clock and data recovery circuit generates a recovery and a reference clock corresponding to the input data and includes a phase shifter generating M discrete clocks at different phases, a data sampler generating a select signal according to the input data and the M discrete clocks, a primary phase selector outputting two consecutive discrete clocks and at least one interpolated clock with a phase between the phases of the two consecutive discrete clocks, a multiplexer selecting one of the two consecutive discrete clocks or the interpolated clock as a selected output clock, a phase detector receiving the selected output clock as the recovery clock and outputting an advanced calibration signal if the recovery clock leads or lags the input data, an advanced phase selector receiving the advanced calibration signal and transmitting the phase select signal to the multiplexer for adjusting the selected output clock and a primary calibration signal.

摘要翻译： 时钟和数据恢复电路产生对应于输入数据的恢复和参考时钟，并包括产生不同相位的M个离散时钟的移相器，根据输入数据和M个离散时钟产生选择信号的数据采样器， 主相位选择器输出两个连续的离散时钟和至少一个具有两个连续离散时钟的相位之间的相位的内插时钟，多路复用器选择两个连续的离散时钟之一或内插时钟作为选择的输出时钟;相位检测器 接收所选择的输出时钟作为恢复时钟，并且如果恢复时钟导致或滞后于输入数据，则输出高级校准信号;高级相位选择器接收高级校准信号并将相位选择信号发送到多路复用器以调整所选择的输出时钟 和主校准信号。

公开(公告)号：US07710207B2

公开(公告)日：2010-05-04

申请号：US11557109

申请日：2006-11-07

申请人： Ching-Yen Wu

发明人： Ching-Yen Wu

IPC分类号： H03B27/00

CPC分类号： H03K3/0322

摘要： A voltage controlled oscillator (VCO) with improved frequency characteristics is provided. The VCO includes a converting circuit supplied between a bias voltage and a ground voltage for converting the control voltage into a control current, a replica bias circuit coupled to the converting circuit for providing a swing voltage, and a ring oscillating circuit coupled to the replica bias circuit having at least two delay units coupled in series for successively delaying an input signal as the oscillating signal after a period of delay time.

摘要翻译： 提供了具有改进的频率特性的压控振荡器（VCO）。 VCO包括在偏置电压和接地电压之间提供的转换电路，用于将控制电压转换成控制电流，耦合到转换电路的复制偏置电路用于提供摆幅电压，以及耦合到复制偏置的环形振荡电路 电路具有串联耦合的至少两个延迟单元，用于在延迟时间段之后连续延迟输入信号作为振荡信号。