EMI rejection for temperature sensing diodes
    31.
    发明授权
    EMI rejection for temperature sensing diodes 有权
    温度感测二极管的EMI抑制

    公开(公告)号:US07622903B2

    公开(公告)日:2009-11-24

    申请号:US11219151

    申请日:2005-09-02

    Inventor: Scott C. McLeod

    CPC classification number: G01K1/00 G01K1/024 G01K7/01

    Abstract: In one set of embodiments, a circuit may be implemented to deliver accurately ratioed currents to a remotely located semiconductor device that has a substantially non-linear input-output characteristic that varies with temperature and is subject to effects of electromagnetic interference (EMI). The circuit may be configured to use common mode rejection by establishing an identical impedance at each of the two terminals of the remotely located semiconductor device, in lieu of coupling shunting capacitor(s) across the terminals, in order to reject EMI signals while performing temperature measurements using the remotely located semiconductor device. This may facilitate maintaining fast sampling times when performing temperature measurements, while providing a more effective method for handling EMI induced currents that may lead to temperature measurement errors, thereby eliminating those errors.

    Abstract translation: 在一组实施例中,可以实现电路以将精确比例的电流传送到远程位置的半导体器件,该半导体器件具有随温度变化并受到电磁干扰(EMI)影响的基本上非线性的输入 - 输出特性。 该电路可以被配置为通过在位于远程的半导体器件的两个端子中的每一个端口处建立相同的阻抗来代替在两个端子之间的耦合分流电容器的同模阻抗,以便在执行温度时抑制EMI信号 使用远程位置的半导体器件进行测量。 这可以有助于在进行温度测量时保持快速采样时间,同时提供更有效的方法来处理可能导致温度测量误差的EMI感应电流,从而消除这些误差。

    Circuit, system, and method for preventing a communication system absent a dedicated clocking master from producing a clocking frequency outside an acceptable range
    32.
    发明授权
    Circuit, system, and method for preventing a communication system absent a dedicated clocking master from producing a clocking frequency outside an acceptable range 有权
    用于防止没有专用时钟主机的通信系统在可接受范围之外产生时钟频率的电路,系统和方法

    公开(公告)号:US07609797B2

    公开(公告)日:2009-10-27

    申请号:US10655265

    申请日:2003-09-04

    CPC classification number: H04L7/0004

    Abstract: A communication system, clock recovery circuit, and method are provided for allowing data to be transmitted across a communication system and between clock recovery circuits absent a clock master specifically designed for one node of the communication system. Absent a clock master, the communication system is permitted to enter into an all slave mode, with periodic unlock conditions possibly rotating about the communication system ring topology. However, the unlock condition can be readily detected and if the received data bitstream formed into a recovered clock exceeds a threshold above or is less than a threshold below a reference clock generated during instances of unlock, then the clock recovery circuit will fix the synchronizing clock to the reference clock, and cause the bitstream to resynchronize to the reference clock before the reference clock is again disabled to allow the communication system to re-enter the all slave and rotating unlock condition. Periodic application of a reference clock interspersed with periodic application of a clock having transitions equal to the incoming bitstream proves advantageous in avoiding a design where a dedicated master must be used within a specified communication system node.

    Abstract translation: 提供一种通信系统,时钟恢复电路和方法,用于允许数据通过通信系统传输,并且在时钟恢复电路之间,而不存在专门为通信系统的一个节点设计的时钟主机。 没有时钟主机,通信系统被允许进入全从机模式,周期性解锁条件可能围绕通信系统环形拓扑旋转。 然而,可以容易地检测到解锁状态,并且如果形成为恢复时钟的接收数据比特流超过了在解锁实例期间产生的参考时钟以下或低于阈值以下的阈值,则时钟恢复电路将固定同步时钟 并且在再次禁用参考时钟之前使比特流重新同步到参考时钟,以允许通信系统重新进入所有从动和旋转解锁状态。 周期性地施加散布有周期性应用具有等于进入比特流的转换的时钟的参考时钟证明有利于避免必须在指定的通信系统节点内使用专用主机的设计。

    Switching upstream and downstream logic between ports in a universal serial bus hub
    33.
    发明授权
    Switching upstream and downstream logic between ports in a universal serial bus hub 有权
    在通用串行总线集线器的端口之间切换上游和下游逻辑

    公开(公告)号:US07480753B2

    公开(公告)日:2009-01-20

    申请号:US11412431

    申请日:2006-04-27

    CPC classification number: G06F13/4022 G06F2213/0042

    Abstract: System and method for switching logic in a Universal Serial Bus hub. The USB hub may include upstream logic and downstream logic for sending and receiving information from a host controller and a USB device respectively. The USB hub may include a plurality of ports operable to couple to a plurality of devices, including a first port coupled to the upstream logic and a second port coupled to the downstream logic. The USB hub may also include switching logic operable to switch the upstream and the downstream logic with respect to the first port and the second port respectively. The switching logic may switch the upstream and downstream logic by decoupling the first port from the upstream logic, decoupling the second port from the downstream logic, and coupling the second port to the upstream logic. Additionally, the first port may be coupled to the downstream logic.

    Abstract translation: 用于在通用串行总线集线器中切换逻辑的系统和方法。 USB集线器可以包括用于分别从主机控制器和USB设备发送和接收信息的上游逻辑和下游逻辑。 USB集线器可以包括可操作以耦合到多个设备的多个端口,包括耦合到上游逻辑的第一端口和耦合到下游逻辑的第二端口。 USB集线器还可以包括可操作以分别相对于第一端口和第二端口切换上游和下游逻辑的交换逻辑。 切换逻辑可以通过将第一端口与上游逻辑解耦来解耦上游和下游逻辑,将第二端口与下游逻辑解耦,并将第二端口耦合到上游逻辑。 另外,第一端口可以耦合到下游逻辑。

    Automatic reference voltage trimming technique
    34.
    发明授权
    Automatic reference voltage trimming technique 有权
    自动参考电压调整技术

    公开(公告)号:US07433790B2

    公开(公告)日:2008-10-07

    申请号:US11145906

    申请日:2005-06-06

    CPC classification number: G01R31/31703 G01R31/3167

    Abstract: In one set of embodiments, trimming of a reference, which may be a bandgap reference and which is configured on an integrated circuit, may be controlled by an algorithm executed by logic circuitry also configured on the integrated circuit. The bandgap reference may be configured to generate a reference voltage provided to an analog to digital converter (ADC) comprised in a temperature sensor that may also be configured on the integrated circuit. The logic circuitry may be configured to execute one or more of a variety of test algorithms, for example a Successive Approximation Method or remainder processing, that are operable to adjust values of reference trim bits used in trimming the bandgap reference. A tester system configured to perform testing of the integrated circuit may initiate execution of the test algorithm, thereby initiating the trimming process, and may wait for the test algorithm to complete within a previously defined amount of time, or may poll the logic circuitry to determine when the trimming process is complete.

    Abstract translation: 在一组实施例中,可以通过由集成电路上也配置的逻辑电路执行的算法来控制可以是带隙基准并且在集成电路上配置的参考的修整。 带隙基准可以被配置为产生提供给也可以在集成电路上配置的温度传感器中的模数转换器(ADC)的参考电压。 逻辑电路可以被配置为执行各种测试算法中的一个或多个,例如连续逼近方法或余数处理,其可操作以调整在修整带隙基准中使用的参考修整位的值。 配置为执行集成电路的测试的测试器系统可以启动测试算法的执行,从而启动修剪过程,并且可以等待测试算法在先前定义的时间量内完成,或者可以轮询逻辑电路以确定 修剪过程完成。

    Proportional settling time adjustment for diode voltage and temperature measurements dependent on forced level current
    35.
    发明授权
    Proportional settling time adjustment for diode voltage and temperature measurements dependent on forced level current 有权
    二极管电压和温度测量的比例建立时间调整取决于强制电平电流

    公开(公告)号:US07429129B2

    公开(公告)日:2008-09-30

    申请号:US11068250

    申请日:2005-02-28

    CPC classification number: G01K7/01

    Abstract: A temperature sensor circuit and system providing accurate digital temperature readings using a local or remote temperature diode. In one set of embodiments a change in diode junction voltage (ΔVBE) proportional to the temperature of the diode is captured and provided to an analog to digital converter (ADC), which may perform required signal conditioning functions on ΔVBE, and provide a digital output corresponding to the temperature of the diode. DC components of errors in the measured temperature that may result from EMI noise modulating the junction voltage (VBE) may be minimized through the use of a front-end sample-and-hold circuit coupled between the diode and the ADC, in combination with a shunt capacitor coupled across the diode junction. The sample-and-hold-circuit may sample VBE at a frequency that provides sufficient settling time for each VBE sample, and provide corresponding stable ΔVBE samples to the ADC at the ADC operating frequency. The ADC may therefore be operated at its preferred sampling frequency rate without incurring reading errors while still averaging out AC components of additional errors induced by sources other than EMI.

    Abstract translation: 温度传感器电路和系统使用本地或远程温度二极管提供精确的数字温度读数。 在一组实施例中,与二极管的温度成比例的二极管结电压(DeltaV BAT)的变化被捕获并提供给模数转换器(ADC),模数转换器(ADC)可执行所需的信号调节功能 并且提供对应于二极管的温度的数字输出。 可以通过使用耦合在二极管之间的前端采样保持电路来最小化可能由EMI噪声调制结电压(V BAT)导致的测量温度中的误差的DC分量 和ADC,与耦合在二极管结上的并联电容器组合。 采样和保持电路可以以为每个V BE样本提供足够的建立时间的频率对V OUT进行采样,并且提供相应的稳定的DeltaV BE< / SUB>采样到ADC的工作频率。 因此,ADC可以以其优选的采样频率运行,而不会引起读取错误,同时仍然对由除EMI之外的源引起的附加误差的AC分量进行平均化。

    Dynamic hysteresis for autofan control
    36.
    发明授权
    Dynamic hysteresis for autofan control 有权
    自动风扇控制的动态滞后

    公开(公告)号:US07394217B2

    公开(公告)日:2008-07-01

    申请号:US11318866

    申请日:2005-12-27

    CPC classification number: G05B11/28

    Abstract: A control signal value, such as a duty cycle value for a Pulse Width Modulated (PWM) generator output, for controlling and/or powering a fan may be calculated using an autofan function configured with dynamic hysteresis control (DHC). As part of the DHC, the PWM duty cycle value may be determined by applying a hysteresis component at every point of the autofan function relating the PWM duty cycle to temperature. The PWM duty cycle value may be computed based on two functions, each function relating the PWM duty cycle to temperature, the first function applied when the temperature is increasing, and the second function applied when the temperature is decreasing. When a newly computed PWM duty cycle value falls within a range of duty cycle values defined by the hysteresis value, the current duty cycle of the PWM generator output may remain unchanged, minimizing noise resulting from the fan changing speed.

    Abstract translation: 可以使用配置有动态滞后控制(DHC)的自动风扇功能来计算用于控制和/或供电风扇的控制信号值,例如用于脉宽调制(PWM)发生器输出的占空比值)。 作为DHC的一部分,可以通过在将PWM占空比与温度相关联的自动功能功能的每个点应用滞后分量来确定PWM占空比值。 可以基于两个功能计算PWM占空比值,每个功能将PWM占空比与温度相关联,当温度升高时应用的第一功能和温度降低时施加的第二功能。 当新计算的PWM占空比值落在由滞后值定义的占空比值的范围内时,PWM发生器输出的当前占空比可保持不变,从而最小化风扇变化速度所产生的噪声。

    Method for implementing a counter in a memory with increased memory efficiency
    37.
    发明授权
    Method for implementing a counter in a memory with increased memory efficiency 有权
    用于在存储器中实现具有增加的存储器效率的计数器的方法

    公开(公告)号:US07369432B2

    公开(公告)日:2008-05-06

    申请号:US11355685

    申请日:2006-02-16

    CPC classification number: G11C16/349 G11C16/102 H03K21/403

    Abstract: A method for implementing a counter in memory, e.g., non-volatile memory such as flash memory. A first number of first binary values indicating a first portion of a current number of the counter in a binary field may be stored in a portion of memory. Storing the first number may also include increasing the number of first binary values in the binary field. Additionally, a second number indicating a second portion of the current number of the counter may be stored in another portion of memory. The second number may specify the number of times the first binary values has comprised the entirety of the binary field. Thus, the first number and second number may specify the current number of the counter. Storing the first and second number may be performed a plurality of times to implement a counting function of the counter.

    Abstract translation: 用于在存储器中实现计数器的方法,例如诸如闪存的非易失性存储器。 指示二进制字段中计数器的当前数量的第一部分的第一二进制值的数量可被存储在存储器的一部分中。 存储第一个数字还可以包括增加二进制字段中的第一二进制值的数量。 此外,指示计数器的当前数量的第二部分的第二数字可以存储在存储器的另一部分中。 第二个数字可以指定第一个二进制值包含整个二进制字段的次数。 因此,第一个数字和第二个数字可以指定计数器的当前编号。 可以多次执行存储第一和第二号码以实现计数器的计数功能。

    Failsafe slave mechanism for mission critical applications
    38.
    发明授权
    Failsafe slave mechanism for mission critical applications 有权
    关键任务应用程序的故障安全从机制

    公开(公告)号:US07305570B2

    公开(公告)日:2007-12-04

    申请号:US10919083

    申请日:2004-08-16

    Abstract: In one embodiment, a monitoring device (e.g., a slave device) may be configured to perform a plurality of monitoring functions. For example, the monitoring device may comprise a watchdog timer configured to monitor communications between the processing unit (e.g., a host processor) and the monitoring device. The watchdog timer may cause the monitoring device to enter a failsafe mode of operation if the processing unit fails to communicate with the monitoring device within a predetermined period of time. Additionally, the monitoring device may be configured to perform thermal management functions via one or more temperature sensors. The monitoring device may enter the failsafe mode of operation if a sensed temperature exceeds a predetermined temperature limit. Furthermore, the monitoring device may also comprise a status unit that is operable to provide the processing unit an indication of a state of the monitoring device.

    Abstract translation: 在一个实施例中,监视设备(例如,从设备)可以被配置为执行多个监视功能。 例如,监视设备可以包括看门狗定时器,其被配置为监视处理单元(例如,主机处理器)与监视设备之间的通信。 如果处理单元在预定时间段内未能与监视设备通信,则看门狗定时器可能导致监视设备进入故障安全操作模式。 此外,监视装置可以被配置为经由一个或多个温度传感器执行热管理功能。 如果感测到的温度超过预定的温度限制,则监测装置可以进入故障安全操作模式。 此外,监视设备还可以包括状态单元,其可操作以向处理单元提供监视设备的状态的指示。

    Method for implementing a counter in a memory with increased memory efficiency
    39.
    发明申请
    Method for implementing a counter in a memory with increased memory efficiency 有权
    用于在存储器中实现具有增加的存储器效率的计数器的方法

    公开(公告)号:US20070189082A1

    公开(公告)日:2007-08-16

    申请号:US11355685

    申请日:2006-02-16

    CPC classification number: G11C16/349 G11C16/102 H03K21/403

    Abstract: A method for implementing a counter in memory, e.g., non-volatile memory such as flash memory. A first number of first binary values indicating a first portion of a current number of the counter in a binary field may be stored in a portion of memory. Storing the first number may also include increasing the number of first binary values in the binary field. Additionally, a second number indicating a second portion of the current number of the counter may be stored in another portion of memory. The second number may specify the number of times the first binary values has comprised the entirety of the binary field. Thus, the first number and second number may specify the current number of the counter. Storing the first and second number may be performed a plurality of times to implement a counting function of the counter.

    Abstract translation: 用于在存储器中实现计数器的方法,例如诸如闪存的非易失性存储器。 指示二进制字段中计数器的当前数量的第一部分的第一二进制值的数量可被存储在存储器的一部分中。 存储第一个数字还可以包括增加二进制字段中的第一二进制值的数量。 此外,指示计数器的当前数量的第二部分的第二数字可以存储在存储器的另一部分中。 第二个数字可以指定第一个二进制值包含整个二进制字段的次数。 因此,第一个数字和第二个数字可以指定计数器的当前编号。 可以多次执行存储第一和第二号码以实现计数器的计数功能。

    EMI rejection for temperature sensing diodes
    40.
    发明申请
    EMI rejection for temperature sensing diodes 有权
    温度感测二极管的EMI抑制

    公开(公告)号:US20070055473A1

    公开(公告)日:2007-03-08

    申请号:US11219151

    申请日:2005-09-02

    Applicant: Scott McLeod

    Inventor: Scott McLeod

    CPC classification number: G01K1/00 G01K1/024 G01K7/01

    Abstract: In one set of embodiments, a circuit may be implemented to deliver accurately ratioed currents to a remotely located semiconductor device that has a substantially non-linear input-output characteristic that varies with temperature and is subject to effects of electromagnetic interference (EMI). The circuit may be configured to use common mode rejection by establishing an identical impedance at each of the two terminals of the remotely located semiconductor device, in lieu of coupling shunting capacitor(s) across the terminals, in order to reject EMI signals while performing temperature measurements using the remotely located semiconductor device. This may facilitate maintaining fast sampling times when performing temperature measurements, while providing a more effective method for handling EMI induced currents that may lead to temperature measurement errors, thereby eliminating those errors.

    Abstract translation: 在一组实施例中,可以实现电路以将精确比例的电流传送到远程位置的半导体器件,该半导体器件具有随温度变化并受到电磁干扰(EMI)影响的基本上非线性的输入 - 输出特性。 该电路可以被配置为通过在位于远程的半导体器件的两个端子中的每一个端口处建立相同的阻抗来代替在两个端子之间的耦合分流电容器的同模阻抗,以便在执行温度时抑制EMI信号 使用远程位置的半导体器件进行测量。 这可以有助于在进行温度测量时保持快速采样时间,同时提供更有效的方法来处理可能导致温度测量误差的EMI感应电流,从而消除这些误差。

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