公开(公告)号：US20130051497A1

公开(公告)日：2013-02-28

申请号：US13219490

申请日：2011-08-26

Applicant: Scott McLeod ,  Nikola Nedovic

Inventor： Scott McLeod ,  Nikola Nedovic

IPC: H04L27/06

CPC classification number: H04B10/695 ,  H04L7/0087 ,  H04L7/033

Abstract: In one embodiment, a receiver may receive a signal from a transmitter. The receiver may include a first sampler that may sample the signal when the value of the signal is zero. The receiver may further include a second sampler that may sample the signal halfway between a time when the first sampler samples the signal and the next time when the first sampler samples the signal to produce a set of sampled values. The receiver may be further operable to determine that a sampled value in the set of sampled values is a logic 1 if the sampled value is greater than the value of a reference voltage and that the sampled value is a logic 0 if the sampled value is less than the value of the reference voltage.

Abstract translation: 在一个实施例中，接收机可以从发射机接收信号。 接收机可以包括当信号的值为零时可以对信号进行采样的第一采样器。 接收机还可以包括第二采样器，其可以在第一采样器对信号进行采样的时间与第一采样器对信号进行采样以产生一组采样值的下一次之间取样信号。 如果采样值大于参考电压的值，则接收机可以进一步可操作以确定采样值集合中的采样值为逻辑1，并且如果采样值较小，采样值为逻辑0 比参考电压的值。

公开(公告)号：US20070215928A1

公开(公告)日：2007-09-20

申请号：US11384961

申请日：2006-03-20

Applicant: Scott McLeod

Inventor： Scott McLeod

IPC: H01L29/94

CPC classification number: H01L23/5223 ,  H01L28/87 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

Abstract: Capacitors configured in a switched-capacitor circuit on a semiconductor device may comprise very accurately matched, high capacitance density metal-to-metal capacitors, using top-plate-to-bottom-plate fringe-capacitance for obtaining the desired capacitance values. A polysilicon plate may be inserted below the bottom metal layer as a shield, and bootstrapped to the top plate of each capacitor in order to minimize and/or eliminate the parasitic top-plate-to-substrate capacitance. This may free up the bottom metal layer to be used in forming additional fringe-capacitance, thereby increasing capacitance density. By forming each capacitance solely based on fringe-capacitance from the top plate to the bottom plate, no parallel-plate-capacitance is used, which may reduce capacitor mismatch. Parasitic bottom plate capacitance to the substrate may also be eliminated, with only a small capacitance to the bootstrapped polysilicon plate remaining. The capacitors may be bootstrapped by coupling the top plate of each capacitor to a respective one of the differential inputs of an amplifier comprised in the switched-capacitor circuit.

Abstract translation: 配置在半导体器件上的开关电容器电路中的电容器可以包括非常精确匹配的高电容密度的金属 - 金属电容器，使用顶板到底板的条纹电容来获得所需的电容值。 可以将多晶硅板插入底部金属层下面作为屏蔽，并且自举到每个电容器的顶板，以便最小化和/或消除寄生的顶板对衬底电容。 这可以释放用于形成额外的边缘电容的底部金属层，从而增加电容密度。 通过仅根据从顶板到底板的边缘电容形成每个电容，不使用平行板电容，这可以减少电容器失配。 也可以消除与衬底的寄生底板电容，仅剩余少量的自举多晶硅板的电容。 电容器可以通过将每个电容器的顶板耦合到开关电容器电路中包括的放大器的差分输入中的相应一个来自举。

公开(公告)号：US08058929B1

公开(公告)日：2011-11-15

申请号：US12777027

申请日：2010-05-10

Applicant: Scott McLeod

Inventor： Scott McLeod

IPC: H03F3/45

CPC classification number: H03F3/45973

Abstract: In one embodiment, a method includes receiving, at a filter comprising a Miller amplifier, a differential data signal output by a limiting amplifier (LA), the data signal comprising an output direct current (DC) offset resulting at least in part from a threshold-adjustment signal applied to the LA or an intrinsic DC offset caused by physical characteristics of the LA. In one embodiment, the method additionally includes generating a compensation signal based on the threshold-adjustment signal, a polarity of the compensation signal being opposite a polarity of the threshold-adjustment signal or the DC offset, a magnitude of the compensation signal being a function of the magnitude of the threshold-adjustment signal. In one embodiment, the method further includes introducing the compensation signal to an internal node of the Miller amplifier to compensate for the DC offset to keep one or more amplifier stages of the Miller amplifier in their linear operating regions.

Abstract translation: 在一个实施例中，一种方法包括在包括米勒放大器的滤波器处接收由限幅放大器（LA）输出的差分数据信号，所述数据信号包括至少部分地从阈值产生的输出直流（DC）偏移 调整信号施加到LA或由LA的物理特性引起的固有DC偏移。 在一个实施例中，该方法还包括基于阈值调整信号产生补偿信号，补偿信号的极性与阈值调整信号或DC偏移的极性相反，补偿信号的幅度是函数 阈值调整信号的大小。 在一个实施例中，该方法还包括将补偿信号引入到米勒放大器的内部节点以补偿DC偏移，以将米勒放大器的一个或多个放大器级保持在它们的线性工作区域中。

公开(公告)号：US20110273233A1

公开(公告)日：2011-11-10

申请号：US12777027

申请日：2010-05-10

Applicant: Scott McLeod

Inventor： Scott McLeod

IPC: H03F3/45

CPC classification number: H03F3/45973

Abstract: In one embodiment, a method includes receiving, at a filter comprising a Miller amplifier, a differential data signal output by a limiting amplifier (LA), the data signal comprising an output direct current (DC) offset resulting at least in part from a threshold-adjustment signal applied to the LA or an intrinsic DC offset caused by physical characteristics of the LA. In one embodiment, the method additionally includes generating a compensation signal based on the threshold-adjustment signal, a polarity of the compensation signal being opposite a polarity of the threshold-adjustment signal or the DC offset, a magnitude of the compensation signal being a function of the magnitude of the threshold-adjustment signal. In one embodiment, the method further includes introducing the compensation signal to an internal node of the Miller amplifier to compensate for the DC offset to keep one or more amplifier stages of the Miller amplifier in their linear operating regions.

Abstract translation: 在一个实施例中，一种方法包括在包括米勒放大器的滤波器处接收由限幅放大器（LA）输出的差分数据信号，所述数据信号包括至少部分地从阈值产生的输出直流（DC）偏移 调整信号施加到LA或由LA的物理特性引起的固有DC偏移。 在一个实施例中，该方法还包括基于阈值调整信号产生补偿信号，补偿信号的极性与阈值调整信号或DC偏移的极性相反，补偿信号的幅度是函数 阈值调整信号的大小。 在一个实施例中，该方法还包括将补偿信号引入到米勒放大器的内部节点以补偿DC偏移，以将米勒放大器的一个或多个放大器级保持在它们的线性工作区域中。

公开(公告)号：US20070024332A1

公开(公告)日：2007-02-01

申请号：US11192152

申请日：2005-07-28

Applicant: Scott McLeod

Inventor： Scott McLeod

IPC: H03L7/00

CPC classification number: H03K17/223

Abstract: A reliable, integrated POR (power-on-reset) circuit with a compact and small area. In one set of embodiments, the POR circuit comprises NMOS and PMOS devices, where a combination of the respective threshold voltages of the NMOS and PMOS devices is used to set the POR threshold. The NMOS and PMOS devices may be coupled in a configuration resulting in a POR threshold that is a function of the PMOS threshold voltage and a scaled version of the NMOS threshold voltage. The scaling factor may be a function of the transconductance parameters of the NMOS and PMOS devices. Additional NMOS devices may be configured in the POR circuit to provide hysteresis functionality, with one of the NMOS devices coupling to one of the original NMOS devices. The scaling factor used in determining the POR threshold in case of a falling supply voltage may then be a function of the transconductance parameters of the original NMOS and PMOS devices and the additional NMOS device coupling to one of the original NMOS devices.

Abstract translation: 可靠的集成POR（上电复位）电路，结构紧凑，占地面积小。 在一组实施例中，POR电路包括NMOS和PMOS器件，其中使用NMOS和PMOS器件的相应阈值电压的组合来设置POR阈值。 NMOS和PMOS器件可以以配置耦合，导致作为PMOS阈值电压和NMOS阈值电压的缩放版本的函数的POR阈值。 缩放因子可以是NMOS和PMOS器件的跨导参数的函数。 可以在POR电路中配置附加的NMOS器件以提供滞后功能，其中NMOS器件之一耦合到原始NMOS器件之一。 在下降的电源电压的情况下用于确定POR阈值的缩放因子然后可以是原始NMOS和PMOS器件的跨导参数和耦合到原始NMOS器件之一的附加NMOS器件的函数。

公开(公告)号：US08803609B2

公开(公告)日：2014-08-12

申请号：US13468769

申请日：2012-05-10

Applicant: Shuo-Chun Kao ,  Scott McLeod

Inventor： Shuo-Chun Kao ,  Scott McLeod

IPC: H03F3/45

CPC classification number: H03F3/45246 ,  H03F3/3022 ,  H03F2203/45248

Abstract: An amplifier may include a gain stage configured to convert an input voltage signal to a current signal and to amplify the input voltage signal according to a gain. The amplifier may also include a buffer stage coupled to the gain stage at an internal node. The buffer stage may be configured to convert the current signal to an output voltage signal and to buffer the current signal from the gain stage so that a frequency bandwidth of the amplifier may be approximately maintained when the gain of the gain stage is increased.

Abstract translation: 放大器可以包括被配置为将输入电压信号转换为电流信号并根据增益来放大输入电压信号的增益级。 放大器还可以包括在内部节点处耦合到增益级的缓冲级。 缓冲级可以被配置为将电流信号转换为输出电压信号并缓冲来自增益级的电流信号，使得当增益级的增益增加时，放大器的频率带宽可以近似保持。

公开(公告)号：US08401045B2

公开(公告)日：2013-03-19

申请号：US13118322

申请日：2011-05-27

Applicant: Scott McLeod ,  Nikola Nedovic

Inventor： Scott McLeod ,  Nikola Nedovic

IPC: H01S3/13

CPC classification number: H01S5/0021 ,  H01S5/183 ,  H04B10/07955

Abstract: In one embodiment, a transmitter can bias a vertical-cavity surface-emitting laser (VCSEL) coupled to an optical medium. The biasing of the VCSEL determines at least in part an optical power output by the VCSEL to the optical medium. The transmitter can also modulate the VCSEL with data to transmit the data optically through the optical medium to a receiver; receive from the receiver through a feedback channel an error vector representing a degradation in performance of the VCSEL sensed by the receiver or an instruction vector comprising one or more coefficients for use in biasing the VCSEL; and adjust the biasing of the VCSEL based on the error vector or the instruction vector to regulate the optical power output by the VCSEL to the optical medium.

Abstract translation: 在一个实施例中，发射器可以偏置耦合到光学介质的垂直腔表面发射激光器（VCSEL）。 VCSEL的偏置至少部分地确定由VCSEL向光学介质输出的光功率。 发射机还可以利用数据对VCSEL进行调制，以通过光学介质光学传输数据到接收机; 从接收机通过反馈信道接收表示由接收机感测的VCSEL的性能下降的误差向量或包括用于偏置VCSEL的一个或多个系数的指令矢量; 并且基于误差矢量或指令矢量调整VCSEL的偏置，以调节VCSEL向光学介质输出的光功率。

公开(公告)号：US20120300801A1

公开(公告)日：2012-11-29

申请号：US13118322

申请日：2011-05-27

Applicant: Scott McLeod ,  Nikola Nedovic

Inventor： Scott McLeod ,  Nikola Nedovic

IPC: H01S3/13

CPC classification number: H01S5/0021 ,  H01S5/183 ,  H04B10/07955

Abstract: In one embodiment, a transmitter can bias a vertical-cavity surface-emitting laser (VCSEL) coupled to an optical medium. The biasing of the VCSEL determines at least in part an optical power output by the VCSEL to the optical medium. The transmitter can also modulate the VCSEL with data to transmit the data optically through the optical medium to a receiver; receive from the receiver through a feedback channel an error vector representing a degradation in performance of the VCSEL sensed by the receiver or an instruction vector comprising one or more coefficients for use in biasing the VCSEL; and adjust the biasing of the VCSEL based on the error vector or the instruction vector to regulate the optical power output by the VCSEL to the optical medium.

Abstract translation: 在一个实施例中，发射器可以偏置耦合到光学介质的垂直腔表面发射激光器（VCSEL）。 VCSEL的偏置至少部分地确定由VCSEL向光学介质输出的光功率。 发射机还可以利用数据对VCSEL进行调制，以通过光学介质光学传输数据到接收机; 从接收机通过反馈信道接收表示由接收机感测的VCSEL的性能下降的误差向量或包括用于偏置VCSEL的一个或多个系数的指令矢量; 并且基于误差矢量或指令矢量调整VCSEL的偏置，以调节VCSEL向光学介质输出的光功率。

公开(公告)号：US20120198578A1

公开(公告)日：2012-08-02

申请号：US13378316

申请日：2010-06-18

Applicant: John William Lowenthal ,  Timothy James Doran ,  Scott Geoffrey Tyack ,  Terry Glenn Wise ,  Scott McLeod

Inventor： John William Lowenthal ,  Timothy James Doran ,  Scott Geoffrey Tyack ,  Terry Glenn Wise ,  Scott McLeod

IPC: C12Q1/70 ,  C07H21/04 ,  A01K67/02

CPC classification number: C12Q1/701 ,  A01K2227/30 ,  A01K2227/40 ,  A01K2267/02 ,  C12N2760/16011 ,  C12N2760/16111 ,  C12Q1/70 ,  C12Q2600/124

Abstract: The present invention relates to an assay for detecting virus, in particular an assay for detecting viral replication in a tissue sample. The invention also relates to methods of determining the susceptibility of an animal to a virus, and methods of breeding animals with decreased susceptibility to a virus.

Abstract translation: 本发明涉及用于检测病毒的测定法，特别是用于检测组织样品中病毒复制的测定法。 本发明还涉及确定动物对病毒的易感性的方法，以及育种对病毒易感性降低的动物的方法。

公开(公告)号：US20070257644A1

公开(公告)日：2007-11-08

申请号：US11429098

申请日：2006-05-05

Applicant: Scott McLeod

Inventor： Scott McLeod

IPC: G05F1/00

CPC classification number: G05F1/565

Abstract: A voltage regulator may include a resistor-based voltage divider circuit generating a desired output voltage from a supply voltage, an output NMOS device whose source terminal may be configured as the output of the voltage regulator and whose drain terminal may be configured to receive the supply voltage, and a control circuit configured to control the output NMOS device to maintain the desired output voltage at the output of the voltage regulator. The control circuit may be configured to receive the desired output voltage from the voltage divider circuit as a first input, and to receive the output of the voltage regulator fed back as a second input to form a feedback loop. The control circuit may control the gate of the output NMOS device via the feedback loop to adjust the output of the voltage regulator by maintaining the desired output voltage at the source of the output NMOS device, and may also clamp the output of the voltage regulator to a specified voltage that is lower than the supply voltage, without requiring a second feedback loop.

Abstract translation: 电压调节器可以包括从电源电压产生期望的输出电压的电阻器分压器电路，输出NMOS器件，其源极端子可以被配置为电压调节器的输出，并且其漏极端子可以被配置为接收电源 电压以及被配置为控制输出NMOS器件以在电压调节器的输出端保持期望的输出电压的控制电路。 控制电路可以被配置为从分压器电路接收期望的输出电压作为第一输入，并且接收作为第二输入反馈的电压调节器的输出以形成反馈回路。 控制电路可以经由反馈回路来控制输出NMOS器件的栅极，以通过在输出NMOS器件的源极处保持期望的输出电压来调节电压调节器的输出，并且还可以将电压调节器的输出钳位到 低于电源电压的指定电压，而不需要第二个反馈回路。