3-D DRAM WORDLINE PARTITION AND STAIRCASE CONTACTS

    公开(公告)号:US20250126774A1

    公开(公告)日:2025-04-17

    申请号:US18403930

    申请日:2024-01-04

    Abstract: Memory devices are provided which have stacked DRAM cells, resulting in an increase in DRAM cell bit-density. In a 3D DRAM with stacked unit cell layers of one or more embodiments, it is necessary to reduce the area of a unit cell in order to increase bit density per unit area for a given number of stacked cells. In one or more embodiments, n wordlines (nWL, n is an integer≥2) share a contact pad. The shared nWLs are separated by n bitlines (BLs) to assign every cell independently one WL and one BL.

    RECONFIGURABLE MAINFRAME WITH REPLACEABLE INTERFACE PLATE

    公开(公告)号:US20250125170A1

    公开(公告)日:2025-04-17

    申请号:US18991285

    申请日:2024-12-20

    Inventor: Michael R. Rice

    Abstract: A mainframe of a device fabrication system comprises a base and a plurality of facets on the base, wherein a first facet of the plurality of facets comprises a first frame comprising a first column on a first side of the first facet, a second column on a second side of the first facet, and a beam connecting the first column to the second column. The mainframe further comprises a lid over the plurality of facets, wherein the base, the lid and the plurality of facets together define an interior volume. A first replaceable interface plate is sealed to the first frame of the first facet. The first column of the first facet comprises a first channel that fluidly couples a first vacuum region associated with the first replaceable interface plate to a vacuum port.

    HEAT TRANSFER JACKETS AND SENSOR ASSEMBLIES, AND RELATED METHODS AND PROCESSING CHAMBERS, FOR SEMICONDUCTOR MANUFACTURING

    公开(公告)号:US20250125164A1

    公开(公告)日:2025-04-17

    申请号:US18487895

    申请日:2023-10-16

    Abstract: The present disclosure relates to heat transfer jackets and sensor assemblies, and related methods and processing chambers, for semiconductor manufacturing. In one or more embodiments, a jacket applicable for semiconductor manufacturing includes one or more outer walls bounding a plurality of fluid channels, and an inner wall at least partially surrounded by at least one of the plurality of fluid channels. The inner wall at least partially defines a receptacle opening. The jacket includes a fluid inlet formed in at least one of the one or more outer walls, a fluid outlet formed in at least one of the one or more outer walls, and a plurality of partition walls separating the plurality of fluid channels. At least one of the plurality of partition walls intersects at least one of the one or more outer walls.

    METHODS TO IMPROVE OXIDE SIDEWALL QUALITY

    公开(公告)号:US20250125145A1

    公开(公告)日:2025-04-17

    申请号:US18485172

    申请日:2023-10-11

    Abstract: Exemplary methods of forming a silicon-containing material may include providing a silicon-containing precursor to a processing region of a semiconductor processing chamber. A substrate may be housed within the processing region of the semiconductor processing chamber and include one or more features. The methods may include generating plasma effluents of the silicon-containing precursor in the processing region. The methods may include depositing a silicon-containing material on a vertically extending portion and a horizontally extending portion of the feature. Methods include soaking the deposited silicon-containing material with a second silicon-containing material.

    GAS FLOW IMPROVEMENT FOR PROCESS CHAMBER

    公开(公告)号:US20250122624A1

    公开(公告)日:2025-04-17

    申请号:US18484767

    申请日:2023-10-11

    Abstract: A process chamber including: a chamber body enclosing an interior volume; a substrate support disposed in the interior volume that includes a lower interior volume below the substrate support and an upper interior volume above the substrate support; a first purge gas line configured to provide a first flow of purge gas to the lower interior volume; and a gas flow ring disposed around an outer edge of the substrate support, the gas flow ring comprising: a ring-shaped body; a top surface; a bottom surface; a first overlapping portion extending from a first inner sidewall of the ring-shaped body; and a second overlapping portion extending from a second inner sidewall of the ring-shaped body. The first overlapping portion is spaced apart from and overlies the second overlapping portion to form a gas flow channel that extends from the bottom surface to the top surface of the gas flow ring.

    PROCESS CHAMBER GAS FLOW IMPROVEMENT

    公开(公告)号:US20250122621A1

    公开(公告)日:2025-04-17

    申请号:US18486291

    申请日:2023-10-13

    Inventor: Zhepeng CONG

    Abstract: A processing system is provided that includes a process chamber. The process chamber includes: a chamber body disposed around a process volume and a substrate support. The processing system further includes a gas supply system coupled to a gas inlet of the process chamber, the gas supply system including: a main gas line connected with the gas inlet of the process chamber. The main gas line includes a first valve configured to open and provide a gas flow path through the main gas line to the process chamber. A first process gas line is connected with the main gas line at a first connection located upstream of the first valve. A second process gas line is connected with the main gas line at a second connection located upstream of the first valve. The main gas line can be separately purged upstream and downstream of the first valve.

    SELF-ALIGNED BIT LINE FOR 4F2 DRAM
    39.
    发明申请

    公开(公告)号:US20250120069A1

    公开(公告)日:2025-04-10

    申请号:US18905062

    申请日:2024-10-02

    Abstract: The present technology includes vertical cell dynamic random-access memory (DRAM) arrays with improve bit line and storage node contact resistivity and self-alignment as well as methods of making such arrays. The arrays include a plurality of bit lines arranged in a first horizontal direction and a plurality of word lines arranged in a second horizontal direction. The arrays include a plurality of channels extending in a vertical direction that is generally orthogonal to the first direction and the second horizontal direction, such that the plurality of bit lines intersect with a source/drain region of the plurality of channels, and the plurality of word lines intersect with gate regions of the plurality of channels. In addition, arrays include where a bit line, a storage node contact, or both, are formed from a metallized material.

    ELECTROSTATICALLY SECURED SUBSTRATE SUPPORT ASSEMBLY

    公开(公告)号:US20250118586A1

    公开(公告)日:2025-04-10

    申请号:US18377752

    申请日:2023-10-06

    Abstract: A substrate support assembly includes a cooling plate and a chuck disposed on the cooling plate. The chuck includes one or more heating electrodes, and one or more clamp electrodes to electrostatically secure the chuck to the cooling plate. Another substrate support assembly includes a cooling plate, a first puck plate bonded to the cooling plate, and a second puck plate disposed on the first puck plate. The second puck plate includes one or more clamp electrodes to electrostatically secure the second puck plate to the first puck plate.

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