公开(公告)号：US08993414B2

公开(公告)日：2015-03-31

申请号：US13938570

申请日：2013-07-10

Applicant: Applied Materials, Inc.

Inventor： Brad Eaton ,  Saravjeet Singh ,  Wei-Sheng Lei ,  Madhava Rao Yalamanchili ,  Tong Liu ,  Ajay Kumar

IPC: H01L21/78 ,  H01L21/3065

CPC classification number: H01L21/67161 ,  B23K26/364 ,  B23K26/40 ,  B23K2103/50 ,  H01J37/32651 ,  H01J37/32788 ,  H01J2237/334 ,  H01L21/3065 ,  H01L21/30655 ,  H01L21/67069 ,  H01L21/67115 ,  H01L21/67742 ,  H01L21/78 ,  Y10T29/5124

Abstract: In embodiments, a hybrid wafer or substrate dicing process involving an initial laser scribe and subsequent plasma etch is implemented for die singulation. The laser scribe process may be used to cleanly remove a mask layer, organic and inorganic dielectric layers, and device layers. The laser etch process may then be terminated upon exposure of, or partial etch of, the wafer or substrate. In embodiments, a multi-plasma etching approach is employed to dice the wafers where an isotropic etch is employed to improve the die sidewall following an anisotropic etch. The isotropic etch removes anisotropic etch byproducts, roughness, and/or scalloping from the anisotropically etched die sidewalls after die singulation.

Abstract translation: 在实施例中，实施涉及初始激光划片和随后的等离子体蚀刻的混合晶片或衬底切割工艺用于裸片切割。 激光划片工艺可用于清洁地去除掩模层，有机和无机介电层以及器件层。 然后可以在曝光或部分蚀刻晶片或衬底时终止激光蚀刻工艺。 在实施例中，采用多等离子体蚀刻方法来骰子晶片，其中采用各向同性蚀刻来改善各向异性蚀刻后的管芯侧壁。 各向同性蚀刻在单片切割之后从各向异性蚀刻的模具侧壁去除各向异性蚀刻副产物，粗糙度和/或扇贝。

公开(公告)号：US20240334683A1

公开(公告)日：2024-10-03

申请号：US18613525

申请日：2024-03-22

Applicant: Applied Materials, Inc.

Inventor： Tong Liu ,  Sony Varghese ,  Zhijun Chen ,  Balasubramanian Pranatharthiharan ,  Anand N. Iyer

IPC: H10B12/00

CPC classification number: H10B12/482 ,  H10B12/02

Abstract: Memory devices and methods of manufacturing memory devices are described herein. The memory devices include a bitline metal stack on a surface comprising a matrix of conductive bitline contacts (e.g., polysilicon) and insulating dielectric islands (e.g., silicon nitride (SiN)). The bitline metal stack comprises one or more of titanium (Ti), tungsten (W), tungsten nitride (WN), tungsten silicide (WS), or tungsten silicon nitride (WSiN). The memory devices include a bitline metal layer (e.g., tungsten (W)) on a top surface of the insulating dielectric islands and on the bitline metal stack.

公开(公告)号：US20250126774A1

公开(公告)日：2025-04-17

申请号：US18403930

申请日：2024-01-04

Applicant: Applied Materials, Inc.

Inventor： Chang Seok Kang ,  Sony Varghese ,  Tong Liu ,  Fredrick Fishburn

IPC: H10B12/00

Abstract: Memory devices are provided which have stacked DRAM cells, resulting in an increase in DRAM cell bit-density. In a 3D DRAM with stacked unit cell layers of one or more embodiments, it is necessary to reduce the area of a unit cell in order to increase bit density per unit area for a given number of stacked cells. In one or more embodiments, n wordlines (nWL, n is an integer≥2) share a contact pad. The shared nWLs are separated by n bitlines (BLs) to assign every cell independently one WL and one BL.

公开(公告)号：US20240373622A1

公开(公告)日：2024-11-07

申请号：US18651117

申请日：2024-04-30

Applicant: Applied Materials, Inc.

Inventor： Tong Liu

IPC: H10B12/00 ,  H01L29/08 ,  H10B12/10

Abstract: Disclosed herein are approaches for forming a 3-D dynamic random-access memory device having reduced floating body effect. In one example, a method may include forming a plurality of layers stacked in a first direction, the plurality of layers including a gate layer formed over a first oxide layer, and a source/drain (S/D) layer between a set of gate oxide layers. The set of gate oxide layers may be formed over the gate layer, and the S/D layer may include a source and a drain on opposite sides of a body. The method may further include forming a doped layer over the source and the drain.