公开(公告)号：US20110149728A1

公开(公告)日：2011-06-23

申请号：US12944472

申请日：2010-11-11

Applicant: Chan Yong LEE

Inventor： Chan Yong LEE

IPC: H04L1/00

CPC classification number: H04W8/26 ,  H04W28/18 ,  H04W88/08

Abstract: A method and apparatus for avoiding a collision of an uplink preamble using a cell identifier. In a case of installing a new small-sized base station in a mobile communication system, the method and apparatus may set a code parameter, a time parameter, and a frequency parameter, differently from a neighboring small-sized base station using the cell identifier even when dedicatedly using a preamble in a contention-free scheme to avoid a collision of the preamble, so that a random access preamble may be managed without occurrence of the collision with the neighboring small-sized base stations.

Abstract translation: 一种用于避免使用小区标识符的上行链路前导码的冲突的方法和装置。 在移动通信系统中安装新的小型基站的情况下，该方法和装置可以使用小区标识符与相邻的小型基站不同地设置码参数，时间参数和频率参数 即使专用于无竞争方案中的前导码以避免前导码的冲突，从而可以管理随机接入前导码而不发生与相邻小型基站的冲突。

公开(公告)号：US20100299652A1

公开(公告)日：2010-11-25

申请号：US12446094

申请日：2007-10-05

Applicant: Chan Yong Lee ,  Nam Hoon Park

Inventor： Chan Yong Lee ,  Nam Hoon Park

IPC: G06F9/44

CPC classification number: G06F9/465 ,  G06F2209/463 ,  H04L29/12141 ,  H04L61/1558

Abstract: An apparatus for managing components in an SCA system includes a naming context tree having one or more directories. Each directory has an ID, the ID is assigned to a component to be registered, and the component is registered in the directory having the ID and unregistered from the directory. The apparatus further includes a name server for managing the components registered in the directories of the naming context tree.

Abstract translation: 用于管理SCA系统中的组件的装置包括具有一个或多个目录的命名上下文树。 每个目录都有一个ID，该ID被分配给要注册的组件，该组件被注册在具有该ID的目录中，并从该目录中注销。 该装置还包括用于管理登记在命名上下文树的目录中的组件的名称服务器。

公开(公告)号：US20100217786A1

公开(公告)日：2010-08-26

申请号：US12682397

申请日：2008-10-10

Applicant: Chan Yong Lee ,  Nam Hoon Park

Inventor： Chan Yong Lee ,  Nam Hoon Park

IPC: G06F17/30

CPC classification number: G06F9/4411 ,  G06F9/4488

Abstract: An apparatus for driving a loadable device component, the apparatus including: the loadable device component providing an application with a loading mechanism that is classified according to a load type property; a core framework module component defining a kind of the load type property; at least one eXtensible Markup Language (XML) data component containing configuration information and generation information of the loadable device component; and a device manager component driving a corresponding loadable device component after parsing the XML data component.

Abstract translation: 一种用于驱动可加载装置部件的装置，该装置包括：可加载装置部件，为应用提供根据负载类型属性分类的装载机构; 定义一种负载类型属性的核心框架模块组件; 至少一个包含所述可加载设备组件的配置信息和生成信息的可扩展标记语言（XML）数据组件; 以及在分析XML数据组件之后驱动相应的可加载设备组件的设备管理器组件。

公开(公告)号：US07525858B2

公开(公告)日：2009-04-28

申请号：US11605974

申请日：2006-11-30

Applicant: Chan-Yong Lee ,  Chi-Wook Kim

Inventor： Chan-Yong Lee ,  Chi-Wook Kim

IPC: G11C7/00

CPC classification number: G11C7/062 ,  G11C7/065 ,  G11C11/4091 ,  G11C2207/063

Abstract: A semiconductor memory device comprises a local sense amplifier connected between a bit line sense amplifier and a current sensing type input/output (IO) sense amplifier. The bit line sense amplifier is connected between a bit line pair, the bit line pair is connected to a local data IO pair, and the local data IO pair is connected to a global data IO pair via a pair of switching circuits. During a read operation of the semiconductor memory device, the local data IO pair remains connected to the global data IO pair.

Abstract translation: 半导体存储器件包括连接在位线读出放大器和电流检测型输入/输出（IO）读出放大器之间的本地读出放大器。 位线读出放大器连接在位线对之间，位线对连接到本地数据IO对，并且本地数据IO对通过一对开关电路连接到全局数据IO对。 在半导体存储器件的读取操作期间，本地数据IO对保持连接到全局数据IO对。

公开(公告)号：US20070280020A1

公开(公告)日：2007-12-06

申请号：US11605974

申请日：2006-11-30

Applicant: Chan-Yong Lee ,  Chi-Wook Kim

Inventor： Chan-Yong Lee ,  Chi-Wook Kim

IPC: G11C7/02

CPC classification number: G11C7/062 ,  G11C7/065 ,  G11C11/4091 ,  G11C2207/063

Abstract: A semiconductor memory device comprises a local sense amplifier connected between a bit line sense amplifier and a current sensing type input/output (IO) sense amplifier. The bit line sense amplifier is connected between a bit line pair, the bit line pair is connected to a local data IO pair, and the local data IO pair is connected to a global data IO pair via a pair of switching circuits. During a read operation of the semiconductor memory device, the local data IO pair remains connected to the global data IO pair.

Abstract translation: 半导体存储器件包括连接在位线读出放大器和电流检测型输入/输出（IO）读出放大器之间的本地读出放大器。 位线读出放大器连接在位线对之间，位线对连接到本地数据IO对，并且本地数据IO对通过一对开关电路连接到全局数据IO对。 在半导体存储器件的读取操作期间，本地数据IO对保持连接到全局数据IO对。

公开(公告)号：US20070018702A1

公开(公告)日：2007-01-25

申请号：US11481518

申请日：2006-07-06

Applicant: Chan-Yong Lee

Inventor： Chan-Yong Lee

IPC: H03L7/06

CPC classification number: H03L7/0812 ,  G11C7/22 ,  G11C7/222 ,  G11C29/02 ,  G11C29/023 ,  G11C2207/2227 ,  H03L7/0802 ,  H03L7/0891

Abstract: A delay-locked loop circuit comprising a variable voltage generator and a delay-locked loop. The variable voltage generator is configured to generate a variable bias voltage signal in response to a standby signal. The variable bias voltage signal has differing voltage levels according to operation modes. The operation modes include a standby mode and an active mode. The delay-locked loop is configured to generate an internal clock signal in response to the standby signal and the variable bias voltage signal. The internal clock signal is synchronized with an external clock signal.

Abstract translation: 一种延迟锁定环路，包括可变电压发生器和延迟锁定环路。 可变电压发生器被配置为响应待机信号产生可变偏置电压信号。 可变偏置电压信号根据操作模式具有不同的电压电平。 操作模式包括待机模式和活动模式。 延迟锁定环路被配置为响应待机信号和可变偏置电压信号产生内部时钟信号。 内部时钟信号与外部时钟信号同步。

公开(公告)号：US07102952B2

公开(公告)日：2006-09-05

申请号：US10915036

申请日：2004-08-10

Applicant: Chan-Yong Lee ,  Jung-Hwa Lee

Inventor： Chan-Yong Lee ,  Jung-Hwa Lee

IPC: G11C5/14

CPC classification number: G11C7/1069 ,  G11C5/14 ,  G11C7/1012 ,  G11C7/1051

Abstract: A semiconductor memory device having a data read path maintains a higher power voltage supplied to an input/output sense amplifier in the input/output path, through which data passes during a data read operation, than the voltage supplied to other circuit components in the data read path, thereby achieving a high data read speed.

Abstract translation: 具有数据读取路径的半导体存储器件在数据读取操作期间保持提供给输入/输出读出放大器的输入/输出读出放大器的电压高于提供给数据中的其它电路元件的电压 读取路径，从而实现高数据读取速度。

公开(公告)号：USD447127S1

公开(公告)日：2001-08-28

申请号：US29131532

申请日：2000-10-24

Applicant: Chan Yong Lee

Designer： Chan Yong Lee