公开(公告)号：US07476585B2

公开(公告)日：2009-01-13

申请号：US11621507

申请日：2007-01-09

Applicant: Chang-Hyun Cho ,  Tae-Young Chung ,  Cheol-Ju Yun ,  Jae-Goo Lee ,  Ju-Yong Lee

Inventor： Chang-Hyun Cho ,  Tae-Young Chung ,  Cheol-Ju Yun ,  Jae-Goo Lee ,  Ju-Yong Lee

IPC: H01L21/8239

CPC classification number: H01L27/10891 ,  H01L27/0207 ,  H01L27/10814 ,  H01L27/10855 ,  H01L28/91

Abstract: A semiconductor device including storage nodes and a method of manufacturing the same: The method includes forming an insulating layer and an etch stop layer on a semiconductor substrate; forming storage node contact bodies to be electrically connected to the semiconductor substrate by penetrating the insulating layer and the etch stop layer; forming landing pads on the etch stop layer to be electrically connected to the storage node contact bodies, respectively; and forming storage nodes on the landing pads, respectively, the storage nodes of which outward sidewalls are completely exposed and which are arranged at an angle to each other.

Abstract translation: 一种包括存储节点的半导体器件及其制造方法，该方法包括在半导体衬底上形成绝缘层和蚀刻停止层; 通过穿透所述绝缘层和所述蚀刻停止层形成要与所述半导体衬底电连接的存储节点接触体; 在所述蚀刻停止层上形成分别电连接到所述存储节点接触体的着陆焊盘; 以及分别在着陆焊盘上形成存储节点，其外侧壁完全暴露的存储节点和彼此成角度地布置。

公开(公告)号：US07321146B2

公开(公告)日：2008-01-22

申请号：US11352179

申请日：2006-02-10

Applicant: Cheol-ju Yun ,  Sun-hoo Park

Inventor： Cheol-ju Yun ,  Sun-hoo Park

IPC: H01L27/108

CPC classification number: H01L27/0207 ,  H01L27/10808 ,  H01L27/10855 ,  H01L27/10885 ,  H01L28/91

Abstract: A DRAM memory cell includes a semiconductor substrate, an interlayer dielectric having storage node contact plugs that is formed on the semiconductor substrate, and storage node electrodes that are formed on the interlayer dielectric to contact the storage node contact plugs. The storage node contact plugs are formed such that an entrance portion is formed to be larger in linewidth than a contacting portions, and they are formed in gaps between the bit line structures. From a plan view perspective, the storage node electrodes of one column are offset from the storage node contact plugs in an adjacent column, such that the storage node electrodes are in a diagonal arrangement throughout the semiconductor substrate.

Abstract translation: DRAM存储单元包括半导体衬底，形成在半导体衬底上的存储节点接触插塞的层间电介质和形成在层间电介质上以与存储节点接触插塞接触的存储节点电极。 存储节点接触插塞形成为使得入口部分形成为比接触部分更大的线宽，并且它们形成在位线结构之间的间隙中。 从平面图的观点来看，一列的存储节点电极偏离相邻列中的存储节点接触插塞，使得存储节点电极在贯穿整个半导体衬底的对角排列。

公开(公告)号：US20070264769A1

公开(公告)日：2007-11-15

申请号：US11769287

申请日：2007-06-27

Applicant: Jin-Woo Lee ,  Cheol-Ju Yun ,  Hyeoung-Won Seo

Inventor： Jin-Woo Lee ,  Cheol-Ju Yun ,  Hyeoung-Won Seo

IPC: H01L21/8242

CPC classification number: H01L27/10814 ,  H01L27/10823 ,  H01L27/10852 ,  H01L27/10873 ,  H01L27/10876 ,  H01L27/10885 ,  H01L27/10888 ,  H01L28/91 ,  H01L29/6659

Abstract: A semiconductor device comprises a plurality of gate structures formed on a substrate, a gate spacer formed on a sidewall of the gate structures, a semiconductor pattern formed on the substrate between the gate structures, a first impurity region and a second impurity region formed in the semiconductor pattern and at surface portions of the substrate, respectively, wherein the first and second impurity regions include a first conductive type impurity, and a channel doping region surrounding the first impurity region, wherein the channel doping region includes a second conductive type impurity.

公开(公告)号：US20070218682A1

公开(公告)日：2007-09-20

申请号：US11751515

申请日：2007-05-21

Applicant: Jae-Goo LEE ,  Cheol-Ju YUN

Inventor： Jae-Goo LEE ,  Cheol-Ju YUN

IPC: H01L21/4763

CPC classification number: H01L27/10888 ,  H01L27/0207 ,  H01L27/10814 ,  H01L27/10855 ,  H01L27/10885

Abstract: Bit lines having first conductive patterns and bit line mask patterns are formed on a first insulating layer between capacitor contact regions of a substrate. An oxide second insulating layer is formed on the bit lines and contact patterns are formed to open storage node contact hole regions corresponding to portions of the second insulating layer. First spacers are formed on sidewalls of the etched portions. The second and first insulating layers are etched to form storage node contact holes exposing the capacitor contact regions. Simultaneously, second spacers of the second insulating layer are formed beneath the first spacers. A second conductive layer fills the storage node contact holes to form storage node contact pads. A loss of the bit line mask pattern decreases due to the reduced thickness of the bit line mask pattern and a bit line loading capacitance decreases due to the second spacers.

Abstract translation: 具有第一导电图案和位线掩模图案的位线形成在衬底的电容器接触区域之间的第一绝缘层上。 在位线上形成氧化物第二绝缘层，并且形成接触图案以打开与第二绝缘层的部分相对应的存储节点接触孔区域。 在蚀刻部分的侧壁上形成第一间隔物。 蚀刻第二和第一绝缘层以形成暴露电容器接触区域的存储节点接触孔。 同时，第二绝缘层的第二间隔件形成在第一间隔件下面。 第二导电层填充存储节点接触孔以形成存储节点接触焊盘。 由于位线掩模图案的厚度减小，位线掩模图案的损失减小，并且位线负载电容由于第二间隔件而减小。

公开(公告)号：US07205232B2

公开(公告)日：2007-04-17

申请号：US10846810

申请日：2004-05-13

Applicant: Cheol-Ju Yun ,  Tae-Young Chung

Inventor： Cheol-Ju Yun ,  Tae-Young Chung

IPC: H01L21/44 ,  H01L23/52

CPC classification number: H01L21/76897 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

Abstract: Disclosed is a method of forming a self-aligned contact structure using a sacrificial mask layer. The method includes forming a plurality of parallel interconnection patterns on a semiconductor substrate. Each of the interconnection patterns has an interconnection and a mask pattern, which are sequentially stacked. Interlayer insulating layer patterns are formed to fill gap regions between the interconnection patterns. The mask patterns are partially etched to form recessed mask patterns that define grooves between the interlayer insulating layer patterns. Then, sacrificial mask patterns filling the grooves are formed. A predetermined region of the interlayer insulating layer patterns is etched using the sacrificial mask patterns as etching masks to form a self-aligned contact hole that exposes a predetermined region of the semiconductor substrate. A spacer is formed of a sidewall of the self-aligned contact hole, and a plug surrounded by the spacer is formed in the self-aligned contact hole.

Abstract translation: 公开了使用牺牲掩模层形成自对准接触结构的方法。 该方法包括在半导体衬底上形成多个平行互连图案。 每个互连图案具有顺序堆叠的互连和掩模图案。 形成层间绝缘层图案以填充互连图案之间的间隙区域。 掩模图案被部分蚀刻以形成在层间绝缘层图案之间限定凹槽的凹陷掩模图案。 然后，形成填充凹槽的牺牲掩模图案。 使用牺牲掩模图案作为蚀刻掩模蚀刻层间绝缘层图案的预定区域，以形成暴露半导体基板的预定区域的自对准接触孔。 间隔件由自对准接触孔的侧壁形成，并且在自对准接触孔中形成由间隔件围绕的塞子。

公开(公告)号：US20060205147A1

公开(公告)日：2006-09-14

申请号：US11430036

申请日：2006-05-09

Applicant: Cheol-Ju Yun ,  Chang-Hyun Cho ,  Tae-Young Chung

Inventor： Cheol-Ju Yun ,  Chang-Hyun Cho ,  Tae-Young Chung

IPC: H01L21/8242

CPC classification number: H01L21/76897 ,  H01L27/10814 ,  H01L27/10855 ,  H01L27/10885 ,  H01L28/91

Abstract: A self-aligned buried contact (BC) pair includes a substrate having diffusion regions; an oxide layer exposing a pair of diffusion regions formed on the substrate; bit lines formed between adjacent diffusion regions and on the oxide layer, each of the bit lines having bit line sidewall spacers formed on sidewalls thereof; a first interlayer dielectric (ILD) layer formed over the bit lines and the oxide layer; a pair of BC pads formed between adjacent bit lines and within the first ILD layer, each BC pad being aligned with one of the pair of exposed diffusion regions in the substrate; and a pair of capacitors, each of the pair of BC pads having one of the pair of capacitors formed thereon, wherein a pair of the bit line sidewall spacers is adjacent to each of the BC pads and the pair of bit line sidewall spacers has an asymmetrical shape.

Abstract translation: 自对准埋层接触（BC）对包括具有扩散区域的衬底; 暴露形成在所述基板上的一对扩散区域的氧化物层; 在相邻扩散区之间和氧化物层上形成的位线，每个位线在其侧壁上形成有位线侧壁间隔物; 形成在位线和氧化物层上的第一层间电介质（ILD）层; 一对BC焊盘，形成在相邻位线之间并在第一ILD层内，每个BC焊盘与衬底中一对暴露的扩散区域中的一个对准; 和一对电容器，所述一对BC焊盘中的每一对具有形成在其上的一对电容器中的一个，其中一对位线侧壁间隔件与每个BC焊盘相邻，并且所述一对位线侧壁间隔件具有 不对称形状。

公开(公告)号：US07026246B2

公开(公告)日：2006-04-11

申请号：US10294683

申请日：2002-11-15

Applicant: Cheol-Ju Yun

Inventor： Cheol-Ju Yun

IPC: H01L21/461

CPC classification number: H01L21/02071 ,  C11D3/3947 ,  C11D7/08 ,  C11D11/0047 ,  H01L21/02074

Abstract: A method of forming a semiconductor device that includes cleaning a substrate after forming a tungsten pattern thereon, comprises forming a tungsten layer on a substrate, etching the tungsten layer to form a tungsten pattern, and performing a cleaning process on the substrate having the tungsten pattern using a cleaning solution of a water solution containing 0.1 to 0.4 wt % fluoric acid and 0.5 to 2 wt % hydrogen peroxide. By using the method of the present invention, metal polymers and oxidized slurry residue generated while forming the tungsten pattern may be completely removed without attacking the tungsten pattern.

Abstract translation: 一种形成半导体器件的方法，包括在其上形成钨图案之后清洁衬底，包括在衬底上形成钨层，蚀刻钨层以形成钨图案，并对具有钨图案的衬底进行清洁处理 使用含有0.1〜0.4重量％氟酸和0.5〜2重量％过氧化氢的水溶液的清洗液。 通过使用本发明的方法，可以完全除去在形成钨图案时产生的金属聚合物和氧化浆料残留物，而不侵蚀钨图案。

公开(公告)号：US20060006410A1

公开(公告)日：2006-01-12

申请号：US11171710

申请日：2005-06-30

Applicant: Jin-Woo Lee ,  Cheol-Ju Yun ,  Hyeoung-Won Seo

Inventor： Jin-Woo Lee ,  Cheol-Ju Yun ,  Hyeoung-Won Seo

IPC: H01L29/45

CPC classification number: H01L27/10814 ,  H01L27/10823 ,  H01L27/10852 ,  H01L27/10873 ,  H01L27/10876 ,  H01L27/10885 ,  H01L27/10888 ,  H01L28/91 ,  H01L29/6659

Abstract: A semiconductor device comprises a plurality of gate structures formed on a substrate, a gate spacer formed on a sidewall of the gate structures, a semiconductor pattern formed on the substrate between the gate structures, a first impurity region and a second impurity region formed in the semiconductor pattern and at surface portions of the substrate, respectively, wherein the first and second impurity regions include a first conductive type impurity, and a channel doping region surrounding the first impurity region, wherein the channel doping region includes a second conductive type impurity.

公开(公告)号：US20050046048A1

公开(公告)日：2005-03-03

申请号：US10762380

申请日：2004-01-23

Applicant: Cheol-Ju Yun ,  Chang-Hyun Cho ,  Tae-Young Chung

Inventor： Cheol-Ju Yun ,  Chang-Hyun Cho ,  Tae-Young Chung

IPC: H01L21/28 ,  H01L21/02 ,  H01L21/60 ,  H01L21/768 ,  H01L21/8242 ,  H01L27/088 ,  H01L27/108 ,  H01L29/417

CPC classification number: H01L21/76897 ,  H01L27/10814 ,  H01L27/10855 ,  H01L27/10885 ,  H01L28/91

Abstract: A self-aligned buried contact (BC) pair includes a substrate having diffusion regions; an oxide layer exposing a pair of diffusion regions formed on the substrate; bit lines formed between adjacent diffusion regions and on the oxide layer, each of the bit lines having bit line sidewall spacers formed on sidewalls thereof; a first interlayer dielectric (ILD) layer formed over the bit lines and the oxide layer; a pair of BC pads formed between adjacent bit lines and within the first ILD layer, each BC pad being aligned with one of the pair of exposed diffusion regions in the substrate; and a pair of capacitors, each of the pair of BC pads having one of the pair of capacitors formed thereon, wherein a pair of the bit line sidewall spacers is adjacent to each of the BC pads and the pair of bit line sidewall spacers has an asymmetrical shape.

Abstract translation: 自对准埋层接触（BC）对包括具有扩散区域的衬底; 暴露形成在所述基板上的一对扩散区域的氧化物层; 在相邻扩散区之间和氧化物层上形成的位线，每个位线在其侧壁上形成有位线侧壁间隔物; 形成在位线和氧化物层上的第一层间电介质（ILD）层; 一对BC焊盘，形成在相邻位线之间并且在第一ILD层内，每个BC焊盘与衬底中一对暴露的扩散区域中的一个对准; 和一对电容器，所述一对BC焊盘中的每一对具有形成在其上的一对电容器中的一个，其中一对位线侧壁间隔件与每个BC焊盘相邻，并且所述一对位线侧壁间隔件具有 不对称形状。