公开(公告)号：US07691719B2

公开(公告)日：2010-04-06

申请号：US11457726

申请日：2006-07-14

申请人： Cheol-Ju Yun ,  Kang-Yoon Lee ,  In-Ho Nam

发明人： Cheol-Ju Yun ,  Kang-Yoon Lee ,  In-Ho Nam

IPC分类号： H01L21/20 ,  H01L21/8242

CPC分类号： H01L21/76885 ,  H01L21/76834 ,  H01L27/10855

摘要： Embodiments of a semiconductor device having storage nodes include an interlayer insulating layer disposed on a semiconductor substrate; a conductive pad disposed in the interlayer insulating layer to contact with a predetermined portion of the substrate, an upper portion of the conductive pad protruding above the interlayer insulating layer; an etch stop layer disposed on the conductive pad and the interlayer insulating layer; and storage nodes penetrating the etch stop layer and disposed on the conductive pad. A penetration path of wet etchant is completely blocked during the wet etch process that removes the mold oxide layer. Therefore, inadvertent etching of the insulating layer due to penetration of wet etchant is prevented, resulting in a stronger, more stable, storage node structure.

摘要翻译： 具有存储节点的半导体器件的实施例包括设置在半导体衬底上的层间绝缘层; 布置在所述层间绝缘层中以与所述基板的预定部分接触的导电焊盘，所述导电焊盘的上部突出于所述层间绝缘层的上方; 设置在所述导电焊盘和所述层间绝缘层上的蚀刻停止层; 并且存储节点穿透蚀刻停止层并且设置在导电焊盘上。 在湿法蚀刻工艺期间，湿蚀刻剂的穿透路径被完全阻挡，从而去除了模具氧化物层。 因此，防止了由于潮湿蚀刻剂的渗透而导致的绝缘层的无意蚀刻，导致更坚固，更稳定的存储节点结构。

公开(公告)号：US20080088025A1

公开(公告)日：2008-04-17

申请号：US11954349

申请日：2007-12-12

申请人： Cheol-ju Yun ,  Tae-young Chung ,  Dong-jun Lee

发明人： Cheol-ju Yun ,  Tae-young Chung ,  Dong-jun Lee

IPC分类号： H01L23/48

CPC分类号： H01L27/10888 ,  H01L21/76804 ,  H01L21/76829 ,  H01L21/76834 ,  H01L21/76897 ,  H01L27/10855 ,  H01L27/10885 ,  H01L27/10891

摘要： A method of manufacturing a semiconductor device includes forming conductive structures on a substrate. Each of the conductive structures has a line shape that extends along a first direction parallel to the substrate. Insulating spacers are formed on upper sidewalls of the conductive structures. An insulating interlayer is formed that covers the conductive structures. A portion of the insulating interlayer between the conductive structures is etched to form a contact hole. An upper portion of the contact hole is larger than a lower portion thereof. The upper portion of the contact hole has a first width along the first direction and a second width along a second direction parallel to the substrate and substantially perpendicular to the first direction. The first width is substantially larger than the second width. The contact hole is filled with a conductive material to form a contact plug.

摘要翻译： 制造半导体器件的方法包括在衬底上形成导电结构。 每个导电结构具有沿平行于基板的第一方向延伸的线状。 绝缘垫片形成在导电结构的上侧壁上。 形成覆盖导电结构的绝缘中间层。 导电结构之间的绝缘中间层的一部分被蚀刻以形成接触孔。 接触孔的上部大于其下部。 接触孔的上部具有沿着第一方向的第一宽度和沿着平行于基底并基本上垂直于第一方向的第二方向的第二宽度。 第一宽度基本上大于第二宽度。 接触孔填充有导电材料以形成接触塞。

公开(公告)号：US07247541B2

公开(公告)日：2007-07-24

申请号：US11171710

申请日：2005-06-30

申请人： Jin-Woo Lee ,  Cheol-Ju Yun ,  Hyeoung-Won Seo

发明人： Jin-Woo Lee ,  Cheol-Ju Yun ,  Hyeoung-Won Seo

IPC分类号： H01L21/336

CPC分类号： H01L27/10814 ,  H01L27/10823 ,  H01L27/10852 ,  H01L27/10873 ,  H01L27/10876 ,  H01L27/10885 ,  H01L27/10888 ,  H01L28/91 ,  H01L29/6659

摘要： A semiconductor device comprises a plurality of gate structures formed on a substrate, a gate spacer formed on a sidewall of the gate structures, a semiconductor pattern formed on the substrate between the gate structures, a first impurity region and a second impurity region formed in the semiconductor pattern and at surface portions of the substrate, respectively, wherein the first and second impurity regions include a first conductive type impurity, and a channel doping region surrounding the first impurity region, wherein the channel doping region includes a second conductive type impurity.

摘要翻译： 半导体器件包括形成在衬底上的多个栅极结构，形成在栅极结构的侧壁上的栅极间隔物，形成在栅极结构之间的衬底上的半导体图案，形成在栅极结构中的第一杂质区域和第二杂质区域 半导体图案和衬底的表面部分，其中第一和第二杂质区域包括第一导电类型杂质和围绕第一杂质区的沟道掺杂区域，其中沟道掺杂区域包括第二导电类型杂质。

公开(公告)号：US07180118B2

公开(公告)日：2007-02-20

申请号：US10830895

申请日：2004-04-22

申请人： Chang-Hyun Cho ,  Tae-Young Chung ,  Cheol-Ju Yun ,  Jae-Goo Lee ,  Ju-Yong Lee

发明人： Chang-Hyun Cho ,  Tae-Young Chung ,  Cheol-Ju Yun ,  Jae-Goo Lee ,  Ju-Yong Lee

IPC分类号： H01L27/108

CPC分类号： H01L27/10891 ,  H01L27/0207 ,  H01L27/10814 ,  H01L27/10855 ,  H01L28/91

摘要： A semiconductor device including storage nodes and a method of manufacturing the same: The method includes forming an insulating layer and an etch stop layer on a semiconductor substrate; forming storage node contact bodies to be electrically connected to the semiconductor substrate by penetrating the insulating layer and the etch stop layer; forming landing pads on the etch stop layer to be electrically connected to the storage node contact bodies, respectively; and forming storage nodes on the landing pads, respectively, the storage nodes of which outward sidewalls are completely exposed and which are arranged at an angle to each other.

摘要翻译： 一种包括存储节点的半导体器件及其制造方法，该方法包括在半导体衬底上形成绝缘层和蚀刻停止层; 通过穿透所述绝缘层和所述蚀刻停止层形成要与所述半导体衬底电连接的存储节点接触体; 在所述蚀刻停止层上形成分别电连接到所述存储节点接触体的着陆焊盘; 以及分别在着陆焊盘上形成存储节点，其外侧壁完全暴露的存储节点和彼此成角度地布置。

公开(公告)号：US07166507B2

公开(公告)日：2007-01-23

申请号：US10774081

申请日：2004-02-05

申请人： Cheol-ju Yun

发明人： Cheol-ju Yun

IPC分类号： H01L21/8242

CPC分类号： H01L27/10814 ,  H01L21/76897 ,  H01L27/10855 ,  H01L27/10885 ,  H01L2924/0002 ,  H01L2924/00

摘要： According to some embodiments of the invention, bit lines are formed using a multi-layered hard mask and BC nodes are separated by forming line-type BCs in the same direction of gate lines. Thus, a narrowing of shoulders between the bit lines and the BCs can be prevented, and spacers can be formed of a low k-dielectric silicon oxide, thereby lowering parasitic capacitance.

摘要翻译： 根据本发明的一些实施例，使用多层硬掩模形成位线，并且通过在栅极线的相同方向上形成线型BC来分离BC节点。 因此，可以防止位线和BC之间的肩部变窄，并且间隔物可以由低k电介质氧化硅形成，从而降低寄生电容。

公开(公告)号：US20070015362A1

公开(公告)日：2007-01-18

申请号：US11457726

申请日：2006-07-14

申请人： Cheol-Ju YUN ,  Kang-Yoon LEE ,  In-Ho NAM

发明人： Cheol-Ju YUN ,  Kang-Yoon LEE ,  In-Ho NAM

IPC分类号： H01L21/302

CPC分类号： H01L21/76885 ,  H01L21/76834 ,  H01L27/10855

摘要： Embodiments of a semiconductor device having storage nodes include an interlayer insulating layer disposed on a semiconductor substrate; a conductive pad disposed in the interlayer insulating layer to contact with a predetermined portion of the substrate, an upper portion of the conductive pad protruding above the interlayer insulating layer; an etch stop layer disposed on the conductive pad and the interlayer insulating layer; and storage nodes penetrating the etch stop layer and disposed on the conductive pad. A penetration path of wet etchant is completely blocked during the wet etch process that removes the mold oxide layer. Therefore, inadvertent etching of the insulating layer due to penetration of wet etchant is prevented, resulting in a stronger, more stable, storage node structure.

摘要翻译： 具有存储节点的半导体器件的实施例包括设置在半导体衬底上的层间绝缘层; 布置在所述层间绝缘层中以与所述基板的预定部分接触的导电焊盘，所述导电焊盘的上部突出于所述层间绝缘层的上方; 设置在所述导电焊盘和所述层间绝缘层上的蚀刻停止层; 并且存储节点穿透蚀刻停止层并且设置在导电焊盘上。 在湿法蚀刻工艺期间，湿蚀刻剂的穿透路径被完全阻挡，从而去除了模具氧化物层。 因此，防止了由于潮湿蚀刻剂的渗透而导致的绝缘层的无意蚀刻，导致更坚固，更稳定的存储节点结构。

公开(公告)号：US20060057783A1

公开(公告)日：2006-03-16

申请号：US11225789

申请日：2005-09-13

申请人： Cheol-ju Yun ,  Bo-sung Kim ,  Huck-jin Kang

发明人： Cheol-ju Yun ,  Bo-sung Kim ,  Huck-jin Kang

IPC分类号： H01L21/82

CPC分类号： H01L23/5258 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of forming a fuse in a semiconductor device can be provided by selectively removing an inter-metal insulator to expose a fuse capping layer by recessing the inter-metal insulator around the fuse and removing the capping layer from the fuse to expose a fuse metal film thereunder.

摘要翻译： 在半导体器件中形成熔丝的方法可以通过选择性地去除金属间绝缘体以通过使金属间绝缘体围绕保险丝凹陷并从保险丝去除覆盖层以暴露熔丝金属熔体来露出熔丝盖层来提供 电影片段。

公开(公告)号：US06916738B2

公开(公告)日：2005-07-12

申请号：US10697722

申请日：2003-10-29

申请人： Jae-Goo Lee ,  Cheol-Ju Yun

发明人： Jae-Goo Lee ,  Cheol-Ju Yun

IPC分类号： H01L21/768 ,  H01L21/4763 ,  H01L21/8242 ,  H01L27/108 ,  H01L29/76

CPC分类号： H01L27/10888 ,  H01L27/0207 ,  H01L27/10814 ,  H01L27/10855 ,  H01L27/10885

摘要： Bit lines having first conductive patterns and bit line mask patterns are formed on a first insulating layer between capacitor contact regions of a substrate. An oxide second insulating layer is formed on the bit lines and contact patterns are formed to open storage node contact hole regions corresponding to portions of the second insulating layer. First spacers are formed on sidewalls of the etched portions. The second and first insulating layers are etched to form storage node contact holes exposing the capacitor contact regions. Simultaneously, second spacers of the second insulating layer are formed beneath the first spacers. A second conductive layer fills the storage node contact holes to form storage node contact pads. A loss of the bit line mask pattern decreases due to the reduced thickness of the bit line mask pattern and a bit line loading capacitance decreases due to the second spacers.

公开(公告)号：US07307305B2

公开(公告)日：2007-12-11

申请号：US11143197

申请日：2005-06-01

申请人： Jae-Goo Lee ,  Cheol-Ju Yun

发明人： Jae-Goo Lee ,  Cheol-Ju Yun

IPC分类号： H01L27/108

CPC分类号： H01L27/10888 ,  H01L27/0207 ,  H01L27/10814 ,  H01L27/10855 ,  H01L27/10885

摘要： Bit lines having first conductive patterns and bit line mask patterns are formed on a first insulating layer between capacitor contact regions of a substrate. An oxide second insulating layer is formed on the bit lines and contact patterns are formed to open storage node contact hole regions corresponding to portions of the second insulating layer. First spacers are formed on sidewalls of the etched portions. The second and first insulating layers are etched to form storage node contact holes exposing the capacitor contact regions. Simultaneously, second spacers of the second insulating layer are formed beneath the first spacers. A second conductive layer fills the storage node contact holes to form storage node contact pads. A loss of the bit line mask pattern decreases due to the reduced thickness of the bit line mask pattern and a bit line loading capacitance decreases due to the second spacers.

摘要翻译： 具有第一导电图案和位线掩模图案的位线形成在衬底的电容器接触区域之间的第一绝缘层上。 在位线上形成氧化物第二绝缘层，并且形成接触图案以打开与第二绝缘层的部分相对应的存储节点接触孔区域。 在蚀刻部分的侧壁上形成第一间隔物。 蚀刻第二和第一绝缘层以形成暴露电容器接触区域的存储节点接触孔。 同时，第二绝缘层的第二间隔件形成在第一间隔件下面。 第二导电层填充存储节点接触孔以形成存储节点接触焊盘。 由于位线掩模图案的厚度减小，位线掩模图案的损失减小，并且位线负载电容由于第二间隔件而减小。

公开(公告)号：US20070111437A1

公开(公告)日：2007-05-17

申请号：US11621507

申请日：2007-01-09

申请人： Chang-Hyun CHO ,  Tae-Young CHUNG ,  Cheol-Ju YUN ,  Jae-Goo LEE ,  Ju-Yong LEE

发明人： Chang-Hyun CHO ,  Tae-Young CHUNG ,  Cheol-Ju YUN ,  Jae-Goo LEE ,  Ju-Yong LEE

IPC分类号： H01L21/8242

CPC分类号： H01L27/10891 ,  H01L27/0207 ,  H01L27/10814 ,  H01L27/10855 ,  H01L28/91

摘要： A semiconductor device including storage nodes and a method of manufacturing the same: The method includes forming an insulating layer and an etch stop layer on a semiconductor substrate; forming storage node contact bodies to be electrically connected to the semiconductor substrate by penetrating the insulating layer and the etch stop layer; forming landing pads on the etch stop layer to be electrically connected to the storage node contact bodies, respectively; and forming storage nodes on the landing pads, respectively, the storage nodes of which outward sidewalls are completely exposed and which are arranged at an angle to each other.

摘要翻译： 一种包括存储节点的半导体器件及其制造方法，该方法包括在半导体衬底上形成绝缘层和蚀刻停止层; 通过穿透所述绝缘层和所述蚀刻停止层形成要与所述半导体衬底电连接的存储节点接触体; 在所述蚀刻停止层上形成分别电连接到所述存储节点接触体的着陆焊盘; 以及分别在着陆焊盘上形成存储节点，其外侧壁完全暴露的存储节点和彼此成角度地布置。