公开(公告)号：US20120186904A1

公开(公告)日：2012-07-26

申请号：US13190586

申请日：2011-07-26

Applicant: Jian-Chun CHENG ,  Bin LIANG ,  Juan TU ,  Xia-Sheng GUO ,  Dong ZHANG

Inventor： Jian-Chun CHENG ,  Bin LIANG ,  Juan TU ,  Xia-Sheng GUO ,  Dong ZHANG

IPC: G10K11/04

CPC classification number: G10K11/04

Abstract: An acoustic diode includes a phononic crystal medium, a nonlinear acoustic medium, a aluminum tubes contain the phononic crystal medium and the nonlinear acoustic medium. The phononic crystal medium is fabricated by alternately laminating a water layers and a glass layers in a periodic manner.

Abstract translation: 声二极管包括声子晶体介质，非线性声学介质，含有声子晶体介质和非线性声学介质的铝管。 声子晶体介质是通过周期性地交替层叠水层和玻璃层来制造的。

公开(公告)号：US20120181714A1

公开(公告)日：2012-07-19

申请号：US13006430

申请日：2011-01-14

Applicant: Chun-Cheng Chang

Inventor： Chun-Cheng Chang

IPC: B29D11/00 ,  B82Y20/00

CPC classification number: G11B7/261

Abstract: Disclosed herein is a method for manufacturing a master plate of an optical disc. The method comprises the step of: (a) forming an inorganic resist layer on a substrate; (b) forming an organic photoresist layer on and in contact with the inorganic resist layer; (c) irradiating both the organic photoresist layer and the inorganic resist layer with a laser beam to form a first exposed region of the inorganic resist layer and a second exposed region of the organic photoresist layer; (d) removing the inorganic resist layer of the first exposed region and the organic photoresist layer of the second exposed region; (e) removing the patterned organic photoresist layer from the patterned inorganic resist layer; (f) conformally forming a release layer to cover the patterned inorganic resist layer; (g) plating a metal layer on the release layer; and (h) separating the metal layer and the release layer.

Abstract translation: 本文公开了一种用于制造光盘的主板的方法。 该方法包括以下步骤：（a）在基板上形成无机抗蚀剂层; （b）在无机抗蚀剂层上并与之接触形成有机光致抗蚀剂层; （c）用激光束照射有机光致抗蚀剂层和无机抗蚀剂层，以形成无机抗蚀剂层的第一曝光区域和有机光致抗蚀剂层的第二曝光区域; （d）除去第一曝光区域的无机抗蚀剂层和第二曝光区域的有机光致抗蚀剂层; （e）从图案化的无机抗蚀剂层上去除图案化的有机光致抗蚀剂层; （f）保形地形成剥离层以覆盖图案化的无机抗蚀剂层; （g）在剥离层上镀覆金属层; 和（h）分离金属层和释放层。

公开(公告)号：US20120173922A1

公开(公告)日：2012-07-05

申请号：US13309598

申请日：2011-12-02

Applicant: Yao-Chun Cheng ,  Yuan-Ning Lien ,  Chuan Yung Liu ,  Feng-I Liu ,  Kuei Huang Liu ,  Michael J. Peters

Inventor： Yao-Chun Cheng ,  Yuan-Ning Lien ,  Chuan Yung Liu ,  Feng-I Liu ,  Kuei Huang Liu ,  Michael J. Peters

IPC: G06F11/14

CPC classification number: G06F11/1417 ,  G06F11/1428 ,  G06F11/2025 ,  G06F11/2038 ,  G06F11/2043

Abstract: An apparatus for handling a failed processor of a multiprocessor system including at least two processors interconnected by processor interconnects for facilitating transactions of the processors. The at least two processors include a first processor set as a default boot processor in response to a boot up operation of the multiprocessor computer, and a second processor. The apparatus includes: a baseboard management module for detecting and receiving health information of the processors; a multiplexer coupled to the baseboard management module and respectively to the processors, the multiplexer being operative to switch between the processors; and a processor ID controller coupled to the baseboard management module and respectively to the processors. In response to the health information indicating the first processor has failed, the processor ID controller sets the second processor as the default boot processor and the baseboard management module enables the multiplexer to switch to the second processor.

Abstract translation: 一种用于处理多处理器系统的故障处理器的装置，包括由处理器互连互连的至少两个处理器，以便于处理器的事务处理。 至少两个处理器包括响应于多处理器计算机的引导操作的第一处理器集合作为默认引导处理器，以及第二处理器。 该装置包括：用于检测和接收处理器的健康信息的基板管理模块; 耦合到所述基板管理模块并分别耦合到所述处理器的多路复用器，所述多路复用器可操作以在所述处理器之间切换; 以及耦合到所述基板管理模块并分别耦合到所述处理器的处理器ID控制器。 响应于指示第一处理器失败的健康信息，处理器ID控制器将第二处理器设置为默认引导处理器，并且基板管理模块使多路复用器切换到第二处理器。

公开(公告)号：US20120171792A1

公开(公告)日：2012-07-05

申请号：US13050956

申请日：2011-03-18

Applicant: Yung-Hui Yeh ,  Chih-Ming Lai ,  Chun-Cheng Cheng

Inventor： Yung-Hui Yeh ,  Chih-Ming Lai ,  Chun-Cheng Cheng

IPC: H01L33/02

CPC classification number: H01L27/1225 ,  H01L27/3262 ,  H01L2251/5338

Abstract: A method of fabricating a pixel array is provided. A first metal layer is formed over a substrate. The metal layer is patterned to form a plurality of data lines and a plurality of drain patterns adjacent to each data line. The data lines and the drain patterns are separated from each other. An oxide semiconductor layer and a first insulation layer covering the oxide semiconductor layer are formed over the substrate. A second metal layer is formed on the first insulation layer and patterned to form a plurality of scan lines intersected with the data lines and the drain patterns. By using the scan lines as a mask, the oxide semiconductor layer and the first insulation layer are patterned to form a plurality of oxide semiconductor channels located under each scan line. Each oxide semiconductor channel is located between one data line and one drain pattern.

Abstract translation: 提供了一种制造像素阵列的方法。 第一金属层形成在衬底上。 图案化金属层以形成与每条数据线相邻的多条数据线和多条漏极图案。 数据线和漏极图案彼此分离。 在基板上形成氧化物半导体层和覆盖氧化物半导体层的第一绝缘层。 第二金属层形成在第一绝缘层上并被图案化以形成与数据线和漏极图案相交的多条扫描线。 通过使用扫描线作为掩模，对氧化物半导体层和第一绝缘层进行图案化以形成位于每条扫描线下方的多个氧化物半导体通道。 每个氧化物半导体沟道位于一个数据线和一个漏极图案之间。

公开(公告)号：US20120156625A1

公开(公告)日：2012-06-21

申请号：US12975081

申请日：2010-12-21

Applicant: Chun-Cheng Chang

Inventor： Chun-Cheng Chang

IPC: G03F7/20 ,  B82Y40/00

CPC classification number: G03F7/0043 ,  G03F7/095

Abstract: Disclosed herein is a nano-fabrication method, which includes the step of: (a) forming an inorganic resist layer on a substrate; (b) forming an organic photoresist layer on the inorganic resist layer; (c) irradiating both the organic photoresist layer and the inorganic resist layer with a laser beam to form a first exposed region of the inorganic resist layer and a second exposed region of the organic photoresist layer; (d) removing the inorganic resist layer of the first exposed region and the organic photoresist layer of the second exposed region to form a patterned inorganic resist layer and a patterned organic photoresist layer; and (e) removing the patterned organic photoresist layer from the patterned inorganic resist layer.

Abstract translation: 本文公开了一种纳米制造方法，其包括以下步骤：（a）在基板上形成无机抗蚀剂层; （b）在无机抗蚀剂层上形成有机光致抗蚀剂层; （c）用激光束照射有机光致抗蚀剂层和无机抗蚀剂层，以形成无机抗蚀剂层的第一曝光区域和有机光致抗蚀剂层的第二曝光区域; （d）去除第一暴露区域的无机抗蚀剂层和第二暴露区域的有机光致抗蚀剂层，以形成图案化无机抗蚀剂层和图案化有机光致抗蚀剂层; 和（e）从图案化的无机抗蚀剂层去除图案化的有机光致抗蚀剂层。

公开(公告)号：US20120092925A1

公开(公告)日：2012-04-19

申请号：US12905100

申请日：2010-10-15

Applicant: Hui-Huang Chen ,  Chih-Yuan Chen ,  Chun-Cheng Chen ,  Ching-Ching Tsai ,  Ting-Jyun He ,  Tai-Liang Hsiung

Inventor： Hui-Huang Chen ,  Chih-Yuan Chen ,  Chun-Cheng Chen ,  Ching-Ching Tsai ,  Ting-Jyun He ,  Tai-Liang Hsiung

IPC: G11C11/34 ,  H01L27/088 ,  G11C7/00

CPC classification number: H01L29/7841 ,  G11C11/404 ,  G11C2211/4016 ,  H01L27/10802 ,  H01L29/749

Abstract: A vertical capacitor-less DRAM cell is described, including: a source layer having a first conductivity type, a storage layer disposed on the source layer and having a second conductivity type, an active layer disposed on the storage layer and having the first conductivity type, a drain layer disposed on the active layer and having the second conductivity type, an address gate disposed beside the active layer and separated from the same by a first gate dielectric layer, and a storage gate disposed beside the storage layer and separated from the same by a second gate dielectric layer. The DRAM cell can be written by turning on the MOSFET formed by the storage layer, the active layer, the drain layer, the first gate dielectric layer and the address gate to inject carriers into the storage layer from the active layer.

Abstract translation: 描述了一种垂直无电容器DRAM单元，包括：具有第一导电类型的源极层，设置在源极层上并具有第二导电类型的存储层，设置在存储层上并具有第一导电类型的有源层 ，设置在有源层上并具有第二导电类型的漏极层，位于有源层旁边并与第一栅极介电层分离的地址栅极和设置在存储层旁边并与其分离的存储栅极 通过第二栅极介电层。 可以通过打开由存储层，有源层，漏极层，第一栅极介电层和地址栅极形成的MOSFET来写入DRAM单元，以将载流子从活性层注入到存储层中。

公开(公告)号：US20120084551A1

公开(公告)日：2012-04-05

申请号：US13250360

申请日：2011-09-30

Applicant: Yao-Chun Cheng ,  Edward Y. Kung ,  Terrence Lee ,  Kuei H. Liu ,  Ming-Hui Pan

Inventor： Yao-Chun Cheng ,  Edward Y. Kung ,  Terrence Lee ,  Kuei H. Liu ,  Ming-Hui Pan

IPC: G06F15/177 ,  G06F1/26

CPC classification number: G06F1/206 ,  Y02D10/16

Abstract: A fan control method for an information handling system is provided. The information handling system includes a device area and a fan for providing air flow to the device area. A plurality of devices is installed on the device area. The method includes the steps of: collecting thermal data of installed devices in the device area when booting up the information handling system; determining a threshold power of the installed devices and a discreteness level of the installed devices based on the thermal data; adjusting an initial speed of the fan based on the discreteness level; and calibrating the speed of the fan to obtain an optimized speed thereof based on the threshold power and the adjusted initial speed. A fan control apparatus for an information handling system is further provided.

Abstract translation: 提供了一种用于信息处理系统的风扇控制方法。 信息处理系统包括用于向设备区域提供空气流的设备区域和风扇。 多个设备安装在设备区域上。 该方法包括以下步骤：在启动信息处理系统时收集设备区域中已安装设备的热数据; 基于热数据确定所安装设备的阈值功率和安装设备的离散水平; 基于离散度调整风扇的初始速度; 并且基于阈值功率和调整后的初始速度来校准风扇的速度以获得其优化的速度。 还提供了一种用于信息处理系统的风扇控制装置。

公开(公告)号：US20120025167A1

公开(公告)日：2012-02-02

申请号：US12845007

申请日：2010-07-28

Applicant: Chen-Fu Chu ,  Feng-Hsu Fan ,  Hao-Chun Cheng ,  Trung Tri Doan

Inventor： Chen-Fu Chu ,  Feng-Hsu Fan ,  Hao-Chun Cheng ,  Trung Tri Doan

IPC: H01L33/04

CPC classification number: H01L33/38 ,  H01L33/32 ,  H01L33/405 ,  H01L33/44 ,  H01L33/641 ,  H01L33/647

Abstract: A vertical light emitting diode (VLED) die includes a metal base; a mirror on the metal base; a p-type semiconductor layer on the reflector layer; a multiple quantum well (MQW) layer on the p-type semiconductor layer configured to emit light; and an n-type semiconductor layer on the multiple quantum well (MQW) layer. The vertical light emitting diode (VLED) die also includes an electrode and an electrode frame on the n-type semiconductor layer, and an organic or inorganic material contained within the electrode frame. The electrode and the electrode frame are configured to provide a high current capacity and to spread current from the outer periphery to the center of the n-type semiconductor layer. The vertical light emitting diode (VLED) die can also include a passivation layer formed on the metal base surrounding and electrically insulating the electrode frame, the edges of the mirror, the edges of the p-type semiconductor layer, the edges of the multiple quantum well (MQW) layer and the edges of the n-type semiconductor layer.

Abstract translation: 垂直发光二极管（VLED）模具包括金属基底; 金属底座上的镜子; 反射层上的p型半导体层; 配置成发光的p型半导体层上的多量子阱（MQW）层; 和多量子阱（MQW）层上的n型半导体层。 垂直发光二极管（VLED）裸片还包括在n型半导体层上的电极和电极框架，以及包含在电极框架内的有机或无机材料。 电极和电极框架被配置为提供高电流容量并且将电流从外周延伸到n型半导体层的中心。 垂直发光二极管（VLED）裸片还可以包括形成在金属基底上的钝化层，该钝化层围绕并电绝缘电极框架，反射镜的边缘，p型半导体层的边缘，多个量子的边缘 （MQW）层和n型半导体层的边缘。

公开(公告)号：US20110316039A1

公开(公告)日：2011-12-29

申请号：US13161254

申请日：2011-06-15

Applicant: WEN-HUANG LIU ,  Chen-Fu Chu ,  Jiunn-Yi Chu ,  Chao-Chen Cheng ,  Hao-Chun Cheng ,  Feng-Hsu Fan ,  Yuan-Hsiao Chang

Inventor： WEN-HUANG LIU ,  Chen-Fu Chu ,  Jiunn-Yi Chu ,  Chao-Chen Cheng ,  Hao-Chun Cheng ,  Feng-Hsu Fan ,  Yuan-Hsiao Chang

IPC: H01L33/40

CPC classification number: H01L33/38 ,  H01L27/15 ,  H01L33/385 ,  H01L33/40 ,  H01L33/44 ,  H01L2224/48091 ,  H01L2224/48465 ,  H01L2224/4903 ,  H01L2924/00014 ,  H01L2924/00

Abstract: Techniques for controlling current flow in semiconductor devices, such as LEDs are provided. For some embodiments, a current guiding structure may be provided including adjacent high and low contact areas. For some embodiments, a second current path (in addition to a current path between an n-contact pad and a metal alloy substrate) may be provided. For some embodiments, both a current guiding structure and second current path may be provided.

Abstract translation: 提供了用于控制诸如LED的半导体器件中的电流的技术。 对于一些实施例，可以提供包括相邻的高和低接触区域的电流引导结构。 对于一些实施例，可以提供第二电流路径（除了n接触焊盘和金属合金衬底之间的电流路径之外）。 对于一些实施例，可以提供电流引导结构和第二电流路径。

公开(公告)号：US08065712B1

公开(公告)日：2011-11-22

申请号：US11138855

申请日：2005-05-25

Applicant: Wen-Chun Cheng ,  Po-Cheng Wang ,  Venkatapathi Raju Srirajavatchavai ,  Rajesh Nair

Inventor： Wen-Chun Cheng ,  Po-Cheng Wang ,  Venkatapathi Raju Srirajavatchavai ,  Rajesh Nair

IPC: G06F7/04 ,  G06F17/30 ,  G06F12/14 ,  G06F17/00 ,  H04L29/06

CPC classification number: H04L63/105 ,  H04L63/08 ,  H04L63/1433 ,  H04L63/145

Abstract: Methods and devices for qualifying a client machine to access a network, based on policies governing required protective measures, such as virus checking and operating system updates, are disclosed. A client machine must pass various checks to qualify for access. A client machine may be redirected to remediation resources that support efforts to bring the client machine into compliance with applicable network access requirements. A policy repository is updated regularly by vendors of protective measures. An administrator establishes user roles that are mapped to policy rule sets retrieved from the policy repository. The policy rule sets govern qualification of client machines for access to the network in accordance with the roles of the users of the machines. An access server is an intermediary between a client machine and the access manager. A client agent runs on the client machine and carries out checks, and reports the results via the access server to the access manager.

Abstract translation: 公开了基于管理所需保护措施（例如病毒检查和操作系统更新）的策略来限定客户机访问网络的方法和设备。 客户端机器必须通过各种检查以符合访问条件。 可以将客户端机器重定向到补救资源，以支持使客户端计算机符合适用的网络访问要求的努力。 保护措施的供应商定期更新政策库。 管理员建立映射到从策略存储库检索的策略规则集的用户角色。 策略规则根据机器用户的角色管理客户机访问网络的资格。 访问服务器是客户机和访问管理器之间的中介。 客户机代理在客户机上运行并执行检查，并通过访问服务器将结果报告给访问管理器。