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公开(公告)号：US07884819B2
公开(公告)日：2011-02-08
申请号：US11535581
申请日：2006-09-27
IPC分类号： G06T15/50
摘要： By merging or adding the color contributions from objects intersected by secondary rays, the image processing system may accumulate color contributions to pixels from objects intersected by secondary rays as the further color contributions are determined. Furthermore, by associating a scaling factor of color contribution with objects and with secondary rays which intersect the objects, color contributions due to secondary ray/object intersections may be calculated at a later time than the color contribution to a pixel from original ray/object intersection. Consequently, it is not necessary for a vector throughput engine or a workload manager to wait for all secondary ray/object intersections to be determined before updating the color of a pixel.
摘要翻译： 通过合并或添加由二次光线相交的物体的颜色贡献，图像处理系统可以累积对由二次光线相交的物体的像素的颜色贡献，因为确定了另外的颜色贡献。 此外，通过将颜色贡献的缩放因子与对象相交，并且与与对象相交的次要光线相关联，可以在比从原始光线/物体交叉点对像素的颜色贡献更晚的时间来计算由于次级光线/物体交叉点引起的颜色贡献 。 因此，在更新像素的颜色之前，矢量吞吐量引擎或工作负载管理器不必等待所有二次光线/物体交叉点的确定。
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公开(公告)号：US07873701B2
公开(公告)日：2011-01-18
申请号：US12102038
申请日：2008-04-14
IPC分类号： G06F15/16
CPC分类号： G06F15/16
摘要： A design structure embodied in a machine readable medium is provided. Embodiments of the design structure include a network on chip (‘NOC’), the NOC comprising: integrated processor (‘IP’) blocks, routers, memory communications controllers, and network interface controller, each IP block adapted to a router through a memory communications controller and a network interface controller, each memory communications controller controlling communication between an IP block and memory, and each network interface controller controlling inter-IP block communications through routers; the network organized into partitions, each partition including at least one IP block, each partition assigned exclusive access to a separate physical memory address space; and one or more applications executing on one or more of the partitions.
摘要翻译： 提供体现在机器可读介质中的设计结构。 该设计结构的实施例包括片上网络（NOC），NOC包括：集成处理器（“IP”）块，路由器，存储器通信控制器和网络接口控制器，每个IP块通过存储器适配于路由器 通信控制器和网络接口控制器，每个存储器通信控制器控制IP块和存储器之间的通信，以及控制通过路由器进行IP间块通信的每个网络接口控制器; 网络组织成分区，每个分区包括至少一个IP块，每个分区分配独占访问单独的物理内存地址空间; 以及在一个或多个分区上执行的一个或多个应用程序。
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公开(公告)号：US20100239186A1
公开(公告)日：2010-09-23
申请号：US12407340
申请日：2009-03-19
CPC分类号： G06T17/005 , G06T15/06 , G06T15/40
摘要： A circuit arrangement, program product and circuit arrangement utilize the known view orientation for an image frame to be rendered to reposition an Accelerated Data Structure (ADS) used during rendering to optimize the generation and/or use of the ADS, e.g., by transforming a scene from which an image frame is rendered to orient the scene relative to the view orientation prior to generating the ADS. A scene may be transformed, for example, to orient the view orientation within a single octant of the scene, with additional processing resources assigned to that octant to ensure sufficient processing resources are devoted to processing the primitives within the view orientation.
摘要翻译： 电路布置，程序产品和电路布置利用已知的视图方向来渲染图像帧以重新定位在渲染期间使用的加速数据结构（ADS），以优化ADS的生成和/或使用，例如通过将 在生成ADS之前，渲染图像帧以使场景相对于视图方向定向的场景。 例如，可以将场景变换为将景物方向定向在场景的单个八分圆内，附加的处理资源被分配给该八分圆，以确保足够的处理资源用于在视图取向中处理图元。
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公开(公告)号：US20090307714A1
公开(公告)日：2009-12-10
申请号：US12135364
申请日：2008-06-09
IPC分类号： G06F9/54
CPC分类号： G06F9/546 , G06F15/7825 , H04L45/00
摘要： Data processing on a network on chip (‘NOC’) that includes IP blocks, routers, memory communications controllers, and network interface controllers; each IP block adapted to a router through a memory communications controller and a network interface controller; each memory communications controller controlling communication between an IP block and memory; each network interface controller controlling inter-IP block communications through routers; each IP block adapted to the network by a low latency, high bandwidth application messaging interconnect comprising an inbox and an outbox; a computer software application segmented into stages, each stage comprising a flexibly configurable module of computer program instructions identified by a stage ID with each stage executing on a thread of execution on an IP block; and at least one of the IP blocks comprising an input/output (‘I/O’) accelerator that administers at least some data communications traffic to and from the at least one IP block.
摘要翻译： 芯片上的数据处理（“NOC”）包括IP块，路由器，存储器通信控制器和网络接口控制器; 每个IP块通过存储器通信控制器和网络接口控制器适应于路由器; 每个存储器通信控制器控制IP块和存储器之间的通信; 每个网络接口控制器通过路由器控制IP间块通信; 每个IP块通过包括收件箱和发件箱的低延迟，高带宽应用消息互连来适应于网络; 每个阶段包括由阶段ID标识的计算机程序指令的灵活可配置模块，每个阶段在IP块上的执行线程上执行; 并且所述IP块中的至少一个包括向所述至少一个IP块执行至少一些数据通信业务的输入/输出（'I / O'）加速器。
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35.发明申请Ordered And Unordered Network-Addressed Message Control With Embedded DMA Commands For A Network On Chip 审中-公开有序和无序的网络寻址消息控制与嵌入式DMA命令为片上网络公开(公告)号：US20090282419A1
公开(公告)日：2009-11-12
申请号：US12118315
申请日：2008-05-09
IPC分类号： G06F9/54
CPC分类号： H04L47/10 , H04L47/34 , H04L49/10 , H04L49/109 , H04L49/90
摘要： Data processing on a network on chip (‘NOC’) that includes integrated processor (‘IP’) blocks, routers, memory communications controllers, network interface controllers, and network-addressed message controllers, with each IP block adapted to a router through a memory communications controller, a network-addressed message controller, and a network interface controller, where each memory communications controller controlling communications between an IP block and memory, each network interface controller controlling inter-IP block communications through routers, with each IP block also adapted to the network by a low latency, high bandwidth application messaging interconnect comprising an inbox and an outbox.
摘要翻译： 包括集成处理器（“IP”）块，路由器，存储器通信控制器，网络接口控制器和网络寻址消息控制器的片上网络（“NOC”）上的数据处理，其中每个IP块通过 存储器通信控制器，网络寻址消息控制器和网络接口控制器，其中每个存储器通信控制器控制IP块和存储器之间的通信，每个网络接口控制器控制通过路由器的IP间块通信，每个IP块也被适配 通过包含收件箱和发件箱的低延迟，高带宽应用消息互连来连接到网络。
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公开(公告)号：US20090282226A1
公开(公告)日：2009-11-12
申请号：US12118039
申请日：2008-05-09
IPC分类号： G06F9/30
CPC分类号： G06F15/7825 , H04L49/109
摘要： A network on chip (‘NOC’) that includes IP blocks, routers, memory communications controllers, and network interface controllers, each IP block adapted to the network by an application messaging interconnect including an inbox and an outbox, one or more of the IP blocks including computer processors supporting a plurality of threads, the NOC also including an inbox and outbox controller configured to set pointers to the inbox and outbox, respectively, that identify valid message data for a current thread; and software running in the current thread that, upon a context switch to a new thread, is configured to: save the pointer values for the current thread, and reset the pointer values to identify valid message data for the new thread, where the inbox and outbox controller are further configured to retain the valid message data for the current thread in the boxes until context switches again to the current thread.
摘要翻译： 包括IP块，路由器，存储器通信控制器和网络接口控制器的片上网络（“NOC”），每个IP块通过包括收件箱和发件箱的应用消息传送互连网络适配到网络，IP网络中的一个或多个 块，包括支持多个线程的计算机处理器，NOC还包括分别设置指向当前线程的有效消息数据的收件箱和发送箱的指针的收件箱和发件箱控制器; 以及在当前线程中运行的软件，在上下文切换到新线程时，配置为：保存当前线程的指针值，并重置指针值以识别新线程的有效消息数据，其中收件箱和 发送箱控制器被进一步配置为将当前线程的有效消息数据保留在框中，直到上下文再次切换到当前线程。
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公开(公告)号：US20090271597A1
公开(公告)日：2009-10-29
申请号：US12108846
申请日：2008-04-24
IPC分类号： G06F9/38
CPC分类号： G06F9/3844 , G06F9/30145 , G06F9/322 , G06F9/3806
摘要： Methods, apparatus, and products for branch prediction in a computer processor are disclosed that include: recording for a sequence of occurrences of a branch, in an algorithm in which the branch occurs more than once, each result of the branch, including maintaining a pointer to a location of a most recently recorded result; resetting the pointer to a location of the first recorded result upon completion of the algorithm; and predicting subsequent results of the branch, in subsequent occurrences of the branch, in dependence upon the recorded results.
摘要翻译： 公开了一种用于在计算机处理器中进行分支预测的方法，装置和产品，包括：在分支出现多于一次的算法中记录分支出现次序，每个分支的结果包括保持指针 到最近记录的结果的位置; 完成算法后，将指针复位到第一记录结果的位置; 并根据记录的结果预测分支的随后的分支结果。
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38.发明申请Network On Chip With A Low Latency, High Bandwidth Application Messaging Interconnect 有权网络片上低延迟，高带宽应用程序消息传递互连公开(公告)号：US20090210592A1
公开(公告)日：2009-08-20
申请号：US12031733
申请日：2008-02-15
CPC分类号： G06F13/4027
摘要： A network on chip (‘NOC’) and methods of data processing on the NOC, the NOC including integrated processor (‘IP’) blocks, a data communications bus (110), memory communications controllers (106), and bus interface controllers (108); each IP block adapted to the data communications bus through a memory communications controller and a bus interface controller; each memory communications controller, in conjunction with one of the bus interface controllers, controlling memory addressed communications between an IP block and memory; each memory communications controller, in conjunction with one of the bus interface controllers, controlling memory addressed communications between one of the IP blocks and other IP blocks; each IP block adapted to the data communications bus by a low latency, high bandwidth application messaging interconnect comprising an inbox and an outbox.
摘要翻译： 片上网络（NOC）和NOC数据处理方法，NOC包括集成处理器（IP）块，数据通信总线（110），存储器通信控制器（106）和总线接口控制器 108）; 每个IP块通过存储器通信控制器和总线接口控制器适应于数据通信总线; 每个存储器通信控制器与一个总线接口控制器一起控制IP块和存储器之间的存储器寻址通信; 每个存储器通信控制器与一个总线接口控制器一起控制IP块和其它IP块之一之间的存储器寻址通信; 每个IP块通过包括收件箱和发件箱的低延迟，高带宽应用消息互连来适应数据通信总线。
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公开(公告)号：US20090135739A1
公开(公告)日：2009-05-28
申请号：US11945396
申请日：2007-11-27
IPC分类号： H04L12/28
CPC分类号： G06F15/7825 , H04L49/109 , H04L49/15 , H04L49/1546 , H04L49/3036 , H04L49/45
摘要： A network on chip (‘NOC’) that includes integrated processor (‘IP’) blocks, routers, memory communications controllers, and network interface controllers, with each IP block adapted to a router through a memory communications controller and a network interface controller, where each memory communications controller controlling communications between an IP block and memory, and each network interface controller controlling inter-IP block communications through routers, with the network organized into partitions, each partition including at least one IP block, each partition assigned exclusive access to a separate physical memory address space and one or more applications executing on one or more of the partitions.
摘要翻译： 包括集成处理器（“IP”）块，路由器，存储器通信控制器和网络接口控制器的片上网络（“NOC”），每个IP块通过存储器通信控制器和网络接口控制器适配于路由器， 其中每个存储器通信控制器控制IP块和存储器之间的通信，以及控制通过路由器的IP间块通信的每个网络接口控制器，其中网络被组织成分区，每个分区包括至少一个IP块，每个分区被分配独占访问 单独的物理内存地址空间和在一个或多个分区上执行的一个或多个应用程序。
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公开(公告)号：US09292965B2
公开(公告)日：2016-03-22
申请号：US12407340
申请日：2009-03-19
CPC分类号： G06T17/005 , G06T15/06 , G06T15/40
摘要： A circuit arrangement, program product and circuit arrangement utilize the known view orientation for an image frame to be rendered to reposition an Accelerated Data Structure (ADS) used during rendering to optimize the generation and/or use of the ADS, e.g., by transforming a scene from which an image frame is rendered to orient the scene relative to the view orientation prior to generating the ADS. A scene may be transformed, for example, to orient the view orientation within a single octant of the scene, with additional processing resources assigned to that octant to ensure sufficient processing resources are devoted to processing the primitives within the view orientation.
摘要翻译： 电路布置，程序产品和电路布置利用已知的视图方向来渲染图像帧以重新定位在渲染期间使用的加速数据结构（ADS），以优化ADS的生成和/或使用，例如通过将 在生成ADS之前，渲染图像帧以使场景相对于视图方向定向的场景。 例如，可以将场景变换为将景物方向定向在场景的单个八分圆内，附加的处理资源被分配给该八分圆，以确保足够的处理资源用于在视图取向中处理图元。
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