公开(公告)号：US20110018064A1

公开(公告)日：2011-01-27

申请号：US12935961

申请日：2009-03-31

申请人： Gerben Doornbos

发明人： Gerben Doornbos

IPC分类号： H01L29/772 ,  H01L21/336

CPC分类号： H01L27/0207 ,  H01L27/11 ,  H01L27/1104

摘要： An SRAM finFET cell includes fins (30 . . . 40) and respective insulated gates (62 . . . 72) forming finFET transistors, together with interconnects (86 . . . 92) connecting the fins and gates. The regions of the fins not covered by the insulated gates are doped. Each of the fins (30 . . . 40) extends in the same longitudinal direction; and each of the fins (30 . . . 40) is arranged laterally adjacent to another fin of the same conductivity type. The cell design reduces the effects of process spread.

摘要翻译： SRAM finFET单元包括形成finFET晶体管的翅片（30 ... 40）和各自的绝缘栅极（62 ... 72），以及连接鳍片和栅极的互连（86.92）。 未被绝缘栅极覆盖的鳍片的区域被掺杂。 每个翅片（30 ...）在相同的纵向方向上延伸; 并且每个翅片（30 ... 40）被布置成与相同导电类型的另一翅片横向相邻。 电池设计减少了工艺扩散的影响。

公开(公告)号：US07839209B2

公开(公告)日：2010-11-23

申请号：US12444140

申请日：2007-10-03

申请人： Gilberto Curatola ,  Prabhat Agarwal ,  Jan W. Slotboom ,  Godefridus A. M. Hurkx ,  Radu Surdeanu ,  Gerben Doornbos

发明人： Gilberto Curatola ,  Prabhat Agarwal ,  Jan W. Slotboom ,  Godefridus A. M. Hurkx ,  Radu Surdeanu ,  Gerben Doornbos

IPC分类号： H01L25/00

CPC分类号： H01L29/161 ,  H01L29/165 ,  H01L29/7391

摘要： A tunnel transistor includes source diffusion (4) of opposite conductivity type to a drain diffusion (6) so that a depletion layer is formed between source and drain diffusions in a lower doped region (8). An insulated gate (16) controls the position and thickness of the depletion layer. The device includes a quantum well formed in accumulation layer (20) which is made of a different material to the lower layer (2) and cap layer (22).

摘要翻译： 隧道晶体管包括与漏扩散（6）相反的导电类型的源极扩散（4），使得在较低掺杂区域（8）中的源极和漏极扩散之间形成耗尽层。 绝缘栅极（16）控制耗尽层的位置和厚度。 该装置包括形成在由下层（2）和盖层（22）的不同材料制成的聚集层（20）中的量子阱。

公开(公告)号：US07791128B2

公开(公告)日：2010-09-07

申请号：US12067986

申请日：2006-09-26

申请人： Gerben Doornbos ,  Pierre Goarin

发明人： Gerben Doornbos ,  Pierre Goarin

IPC分类号： H01L29/788

CPC分类号： H01L29/7881 ,  H01L21/28273 ,  H01L21/28282 ,  H01L29/42324 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/785

摘要： The present invention relates to a non-volatile memory device on a substrate layer comprising semiconductor source and drain regions, a semiconductor channel region, a charge storage stack and a control gate; the channel region being fin-shaped having two sidewall portions and a top portion, and extending between the source region and the drain region; the charge storage stack being positioned between the source and drain regions and extending over the fin-shaped channel, substantially perpendicularly to the length direction of the fin-shaped channel; the control gate being in contact with the charge storage stack, wherein—an access gate is provided adjacent to one sidewall portion and separated therefrom by an intermediate gate oxide layer, and—the charge storage stack contacts the fin-shaped channel on the other sidewall portion and is separated from the channel by the intermediate gate oxide layer.

摘要翻译： 本发明涉及包括半导体源极和漏极区域的衬底层上的非易失性存储器件，半导体沟道区域，电荷存储堆叠和控制栅极; 所述通道区域是翅片状的，具有两个侧壁部分和顶部部分，并且在所述源极区域和所述漏极区域之间延伸; 所述电荷存储堆叠位于所述源极和漏极区域之间并且在所述鳍状通道上延伸，基本上垂直于所述鳍状通道的长度方向; 所述控制栅极与所述电荷存储堆叠接触，其中，接近栅极邻近一个侧壁部分设置并且由中间栅极氧化物层与其隔开，并且所述电荷存储堆叠接触所述另一个侧壁上的所述鳍状沟道 并且通过中间栅极氧化物层与沟道分离。