公开(公告)号：US08362821B2

公开(公告)日：2013-01-29

申请号：US12743400

申请日：2008-11-12

申请人： Tony Vanhoucke ,  Godefridus A. M. Hurkx ,  Jan W. Slotboom

发明人： Tony Vanhoucke ,  Godefridus A. M. Hurkx ,  Jan W. Slotboom

IPC分类号： H03K17/00 ,  H03K17/60

CPC分类号： G11C13/0004

摘要： An electronic device comprising a generator for generating a stream of charge carriers. The generator comprises a bipolar transistor having an emitter region, a collector region and a base region oriented between the emitter region and the collector region, and a controller for controlling exposure of the bipolar transistor to a voltage in excess of its open base breakdown voltage (BVCEO) such that the emitter region generates the stream of charge carriers from a first area being smaller than the emitter region surface area. The electronic device may further comprise a material arranged to receive the stream of charge carriers for triggering a change in a property of said material, the emitter region being arranged between the base region and the material.

摘要翻译： 一种电子设备，包括用于产生电荷载流子的发生器。 发生器包括双极晶体管，其具有发射极区域，集电极区域和定向在发射极区域和集电极区域之间的基极区域;以及控制器，用于控制双极晶体管的暴露于超过其开路基极击穿电压的电压（ BVCEO），使得发射极区域从小于发射极区域表面积的第一区域产生电荷载流子。 电子设备还可以包括布置成接收电荷载流子的材料，用于触发所述材料的性质的变化，发射极区域布置在基底区域和材料之间。

公开(公告)号：US20100038676A1

公开(公告)日：2010-02-18

申请号：US12177258

申请日：2008-07-22

申请人： Anco Heringa ,  Raymond J.E. Hueting ,  Jan W. Slotboom

发明人： Anco Heringa ,  Raymond J.E. Hueting ,  Jan W. Slotboom

IPC分类号： H01L29/74

CPC分类号： H01L29/7802 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/402 ,  H01L29/408 ,  H01L29/73 ,  H01L29/732 ,  H01L29/7811 ,  H01L29/7813 ,  H01L29/7824 ,  H01L29/861

摘要： A semiconductor device includes a semiconductor region having a pn junction and a field shaping region located adjacent the pn junction to increase the reverse breakdown voltage of the device. The field shaping region is coupled via capacitive voltage coupling regions to substantially the same voltages as are applied to the pn junction. When a reverse voltage is applied across the pn junction and the device is non-conducting, a capacitive electric field is present in a part of the field shaping region which extends beyond a limit of the pn junction depletion region which would exist in the absence of the field shaping region. The electric field in the field shaping region inducing a stretched electric field limited to a correspondingly stretched pn junction depletion region in the semiconductor region.

摘要翻译： 半导体器件包括具有pn结的半导体区域和位于pn结附近的场整形区域，以增加器件的反向击穿电压。 场整形区域经由电容性电压耦合区域耦合到与施加到pn结的基本相同的电压。 当在pn结上施加反向电压并且器件不导通时，在场成形区域的一部分中存在电容电场，其延伸超过不存在pn结区域的pn结耗尽区的极限 场整形区域。 场成形区域中的电场引起限制在半导体区域中相应延伸的pn结耗尽区的拉伸电场。

公开(公告)号：US20080258182A1

公开(公告)日：2008-10-23

申请号：US11577311

申请日：2005-10-13

申请人： Prabhat Agarwal ,  Jan W. Slotboom ,  Wibo Van Noort

发明人： Prabhat Agarwal ,  Jan W. Slotboom ,  Wibo Van Noort

IPC分类号： H01L29/808 ,  H01L21/8232 ,  H01L21/337

CPC分类号： H01L27/098 ,  H01L21/8248 ,  H01L27/0623

摘要： A BiCMOS-compatible JFET device comprising source and drain regions (17, 18) which are formed in the same process as that used to form the emitter out-diffusion or a vertical bipolar device, wherein the semiconductor layer which forms the emitter cap in the bipolar device forms the channel (16) of the JFET device and the layer of material (i.e. the base epi-stack) which forms the intrinsic base region of the bipolar device forms the intrinsic gate region (14) of the JFET device. As a result, the integration of the JFET device into a standard BiCMOS process can be achieved without the need for any additional masking or other processing steps.

摘要翻译： 一种BiCMOS兼容的JFET器件，包括以与用于形成发射极外扩散的相同的工艺形成的源极和漏极区域（17,18），或者垂直双极器件，其中形成发光极帽的半导体层 双极器件形成JFET器件的沟道（16），并且形成双极器件的本征基极区域的材料层（即，基极外延堆叠）形成JFET器件的本征栅极区域（14）。 结果，可以实现JFET器件到标准BiCMOS工艺的集成，而不需要任何额外的掩模或其他处理步骤。

公开(公告)号：US20080144355A1

公开(公告)日：2008-06-19

申请号：US11720320

申请日：2005-11-24

申请人： Hans M.B. Boeve ,  Karen Attenborough ,  Godefridus A.M. Hurkx ,  Prabhat Agarwal ,  Hendrik G.A. Huizing ,  Michael A.A. In'T Zandt ,  Jan W. Slotboom

发明人： Hans M.B. Boeve ,  Karen Attenborough ,  Godefridus A.M. Hurkx ,  Prabhat Agarwal ,  Hendrik G.A. Huizing ,  Michael A.A. In'T Zandt ,  Jan W. Slotboom

IPC分类号： G11C17/18 ,  G11C11/00 ,  H01L21/326 ,  H01L29/02

CPC分类号： G11C11/5678 ,  G11C13/0004 ,  H01L27/2409 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/1246 ,  H01L45/144

摘要： A thermally programmable memory has a programmable element (20) of a thermally programmable resistance preferably of phase change material, material and a blown antifuse (80) located adjacent to the programmable material. Such a blown antifuse has a dielectric layer (100) surrounded by conductive layers (90, 110) to enable a brief high voltage to be applied across the dielectric to blow a small hole in the dielectric during manufacture to form a small conductive path which can be used as a tiny electrical heater for programming the material. Due to the current confinement by the hole, the volume of the material that must be heated in order to switch to a highly-resistive state is very small. As a result the programming power can be low.

摘要翻译： 热可编程存储器具有可编程电阻的可编程电阻（20），优选地是相变材料的材料和位于可编程材料附近的吹制反熔丝（80）。 这种吹制的反熔丝具有由导电层（90,110）包围的电介质层（100），以使得能够在制造期间在电介质两端施加短暂的高电压来吹动电介质中的小孔，以形成小导电路径， 用作编程材料的微小电加热器。 由于目前由孔的限制，为了切换到高电阻状态必须被加热的材料的体积非常小。 因此，编程功率可能很低。

公开(公告)号：US06774434B2

公开(公告)日：2004-08-10

申请号：US10293993

申请日：2002-11-12

申请人： Raymond J. E. Hueting ,  Jan W. Slotboom ,  Petrus H. C. Magnee

发明人： Raymond J. E. Hueting ,  Jan W. Slotboom ,  Petrus H. C. Magnee

IPC分类号： H01L2976

CPC分类号： H01L29/7813 ,  H01L29/0653 ,  H01L29/405 ,  H01L29/407 ,  H01L29/408 ,  H01L29/4236 ,  H01L29/66696 ,  H01L29/66727 ,  H01L29/7395 ,  H01L29/7722 ,  H01L29/7787 ,  H01L29/7803 ,  H01L29/7806 ,  H01L29/7824 ,  H01L29/7825 ,  H01L29/812 ,  H01L29/8122

摘要： A field effect transistor semiconductor device (1) comprises a source region (33), a drain region (14) and a drain drift region (11), the device having a field shaping region (20) adjacent the drift region (11) and arranged such that, in use, when a voltage is applied between the source (33) and drain (14) regions and the device is non-conducting, a substantially constant electric field is generated in the field shaping region (20) and accordingly in the adjacent drift region (11). The field shaping region (20), which may be intrinsic semiconductor, is arranged to function as a capacitor dielectric region (20) between a first capacitor electrode region (21) and a second capacitor electrode region (22), the first and second capacitor electrode regions (21, 22) being adjacent respective ends of the dielectric region (20) and having different electron energy barriers. The first and second capacitor electrode regions (21, 22) may be opposite conductivity semiconductor regions, or they may be a semiconductor region (21) and a Schottky barrier region (224, FIG. 4). The device may be an insulated gate device (1, 13, 15, 17, 171, 172, 19, 12) particularly suitable for high or low voltage DC power applications, or a Schottky gate device (181, 182, 183) particularly suitable for RF applications.

摘要翻译： 场效应晶体管半导体器件（1）包括源极区（33），漏极区（14）和漏极漂移区（11），该器件具有与漂移区（11）相邻的场整形区（20）和 被布置为使得在使用中，当在源极（33）和漏极（14）区域之间施加电压并且器件不导通时，在场成形区域（20）中产生基本恒定的电场，因此在 相邻的漂移区域（11）。 可以将本征半导体的场成形区域（20）布置成用作第一电容器电极区域（21）和第二电容器电极区域（22）之间的电容器介电区域（20），第一和第二电容器 电极区域（21,22）与电介质区域（20）的相应端部相邻并且具有不同的电子能量势垒。 第一和第二电容器电极区域（21,22）可以是相反的导电半导体区域，或者它们可以是半导体区域（21）和肖特基势垒区域（224，图4）。 该器件可以是特别适用于高压或低压DC电源应用的绝缘栅极器件（1,13,15,17,171,172,19,12），或特别合适的肖特基栅极器件（181,182,183） 用于射频应用。

公开(公告)号：US4599710A

公开(公告)日：1986-07-08

申请号：US605958

申请日：1984-05-01

申请人： Marcellinus J. M. Pelgrom ,  Johannes G. Raven ,  Jan W. Slotboom ,  Hendrik A. Harwig ,  Marcellinus J. J. C. Annegarn

发明人： Marcellinus J. M. Pelgrom ,  Johannes G. Raven ,  Jan W. Slotboom ,  Hendrik A. Harwig ,  Marcellinus J. J. C. Annegarn

IPC分类号： H04N5/907 ,  G11C5/06 ,  G11C7/00 ,  G11C7/22 ,  G11C8/18 ,  G11C11/401 ,  G11C19/28

CPC分类号： G11C19/285 ,  G11C5/066 ,  G11C7/22 ,  G11C8/18

摘要： In a series-parallel-series memory circuit (3) which requires a write clock signal (at 19), a transfer clock signal (at 25) and a read clock signal (at 31), it is sufficient, because a clock signal processing circuit (23) is provided, to apply only two clock signals (to 33 and 35). Using a gate circuit (41), it is possible to obtain from one clock signal (applied to 35) additional information, which is provided by means of pulse duration variation, for adapting the time delay of the memory circuit (FIG. 1).

摘要翻译： 在需要写入时钟信号（at 19），传输时钟信号（25）和读取时钟信号（31））的串并联串行存储器电路（3）中，由于时钟信号处理 提供电路（23），仅施加两个时钟信号（至33和35）。 使用门电路（41），可以从一个时钟信号（施加到35）获得由脉冲持续时间变化提供的附加信息，以适应存储器电路（图1）的时间延迟。

公开(公告)号：US07423299B2

公开(公告)日：2008-09-09

申请号：US10556802

申请日：2004-05-06

申请人： Anco Heringa ,  Raymond J. E. Hueting ,  Jan W. Slotboom

发明人： Anco Heringa ,  Raymond J. E. Hueting ,  Jan W. Slotboom

IPC分类号： H01L29/74

CPC分类号： H01L29/7802 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/402 ,  H01L29/408 ,  H01L29/73 ,  H01L29/732 ,  H01L29/7811 ,  H01L29/7813 ,  H01L29/7824 ,  H01L29/861

摘要： A semiconductor device, for example a diode (200), having a pn junction (101) has an insulating material field shaping region (201) adjacent, and possibly bridging, the pn junction. The field shaping region (201) preferably has a high dielectric constant and is coupled via capacitive voltage coupling regions (204,205) to substantially the same voltages as are applied to the pn junction. When a reverse voltage is applied across the pn junction (101) and the device is non-conducting, a capacitive electric field, is present in a part of the field shaping region which extends beyond a limit of the pn junction depletion region which would exist in the absence of the field shaping region (201), the electric field in the field shaping region inducing a stretched electric field limited to a correspondingly stretched pn junction depletion region (208,209) and an increased reverse breakdown voltage of the device.

摘要翻译： 具有pn结（101）的半导体器件（例如二极管（200））具有与pn结相邻且可能桥接的绝缘材料场整形区域（201）。 场成形区域（201）优选地具有高介电常数，并且经由电容性电压耦合区域（204,205）耦合到与施加到pn结的基本相同的电压。 当在pn结（101）上施加反向电压并且器件不导通时，电容电场存在于场成形区域的一部分中，其延伸超过将存在的pn结耗尽区的极限 在不存在场整形区域（201）的情况下，场成形区域中的电场引起限制到相应延伸的pn结耗尽区域（208,209）的拉伸电场和该器件的反向击穿电压的增加。

公开(公告)号：US06777780B2

公开(公告)日：2004-08-17

申请号：US10205555

申请日：2002-07-25

申请人： Raymond J. E. Hueting ,  Jan W. Slotboom ,  Petrus H. C. Magnee

发明人： Raymond J. E. Hueting ,  Jan W. Slotboom ,  Petrus H. C. Magnee

IPC分类号： H01L27082

CPC分类号： H01L29/402 ,  H01L29/0821 ,  H01L29/405 ,  H01L29/407 ,  H01L29/73 ,  H01L29/7371 ,  H01L29/739

摘要： The invention relates to a trench bipolar transistor structure, having a base 7, emitter 9 and collector 4, the latter being divided into a higher doped region 3 and a lower doped drift region 5. An insulated gate 11 is provided to deplete the drift region 5 when the transistor is switched off. The gate 11 and/or doping levels in the drift region 5 are arranged to provide a substantially uniform electric field in the drift region in this state, to minimise breakdown. In particular, the gate 11 may be seminsulating and a voltage applied along the gate between connections 21,23.

摘要翻译： 本发明涉及一种沟槽双极晶体管结构，其具有基极7，发射极9和集电极4，后者被分成较高掺杂区3和下掺杂漂移区5.绝缘栅11被设置成消耗漂移区 5当晶体管关闭时。 漂移区5中的栅极11和/或掺杂电平被布置成在该状态下在漂移区中提供基本上均匀的电场，以最小化破坏。 特别地，栅极11可以是半绝缘的，并且沿连接21,23之间的栅极施加电压。

公开(公告)号：US5502326A

公开(公告)日：1996-03-26

申请号：US381002

申请日：1995-01-25

申请人： Jan W. Slotboom ,  Pierre H. Woerlee ,  Reinout Woltjer

发明人： Jan W. Slotboom ,  Pierre H. Woerlee ,  Reinout Woltjer

IPC分类号： H01L27/10 ,  G11C17/16 ,  H01L21/8246 ,  H01L23/525 ,  H01L27/102 ,  H01L27/112 ,  H01L29/00 ,  H01L27/095

CPC分类号： G11C17/16 ,  H01L23/5252 ,  H01L2924/0002 ,  Y10S257/91

摘要： A semiconductor device includes a programmable element having a doped semiconductor region (4) and a conductor region (6) which are separated from one another by at least a portion of an insulating layer (5). The conductor region (6) is of a material suitable for forming a rectifying junction (8) with the material of the semiconductor region (4). To achieve a comparatively high conductivity connection to the semiconductor region (4), the element is further provided with a contact region (3) which has a comparatively low electrical resistance compared with the semiconductor region (4). The contact region (3) is provided at a side of the semiconductor region (4) remote from the insulating layer (5) and is separated from the insulating layer (5) by the semiconductor region (4). Both the semiconductor region (4) and the contact region (5) are laterally bounded by an isolating region (7) at opposing sides. The invention thus offers a device provided with a programmable element of a substantially more compact structure than a comparable conventional programmable element.

摘要翻译： 半导体器件包括具有掺杂半导体区域（4）的可编程元件和通过绝缘层（5）的至少一部分彼此分离的导体区域（6）。 导体区域（6）是适于与半导体区域（4）的材料形成整流结（8）的材料。 为了实现与半导体区域（4）的较高的导电性连接，元件还具有与半导体区域（4）相比具有相对低的电阻的接触区域（3）。 接触区域（3）设置在远离绝缘层（5）的半导体区域（4）的一侧，并且通过半导体区域（4）与绝缘层（5）分离。 半导体区域（4）和接触区域（5）都由相对侧的隔离区域（7）横向界定。 因此，本发明提供了一种具有比可比较的常规可编程元件基本上更紧凑结构的可编程元件的装置。

公开(公告)号：US4998153A

公开(公告)日：1991-03-05

申请号：US263662

申请日：1988-10-27

申请人： Karel E. Kuyk ,  Jan W. Slotboom ,  Geert J. T. Davids ,  Wiegert Wiertsema ,  Arie Slob

发明人： Karel E. Kuyk ,  Jan W. Slotboom ,  Geert J. T. Davids ,  Wiegert Wiertsema ,  Arie Slob

IPC分类号： H01L27/10 ,  G11C19/28 ,  G11C27/04 ,  H01L21/339 ,  H01L21/8242 ,  H01L27/108 ,  H01L27/148 ,  H01L29/762 ,  H01L29/768 ,  H04N5/335

CPC分类号： H01L29/76816 ,  G11C19/287 ,  G11C27/04

摘要： A first charge storage electrode (21) has a first row (21b) of teeth interdigitated with a second row (22b) of teeth of a second charge storage electrode (22). The second storage electrode (22) has a third row (22c) of teeth interdigitated with a fourth row (23b) of teeth of a third charge storage electrode (23). The first and third rows (21b and 22c) overlie one group (11b) of a series of parallel conduction channels while the second and fourth rows (22b and 23b) overlie another group (11a) of the parallel channels. A first charge transfer electrode (24) is provided to transfer charge packets into sites beneath the first storage electrode. Second, third, fourth and fifth charge transfer electrodes (25, 26, 27 and 28) are provided to transfer charge packets between sites beneath, respectively, the first storage electrode (21) and the second row (22b), the first row (21b) and the second storage electrode (22), the second storage electrode (22) and the fourth row (23b), and the third row (22c) and the third storage electrode (23). The first, second and third storage and associated transfer electrodes may form an output stage (20) of a parallel register (C) of a series-parallel-series device to enable de-interlacing of rows of information.