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公开(公告)号:US12271807B2
公开(公告)日:2025-04-08
申请号:US17250892
申请日:2019-05-21
Inventor: Xiaowei Li , Xin Wei , Hang Lu
Abstract: Disclosed embodiments relate to a convolutional neural network computing method and system based on weight kneading, comprising: arranging original weights in a computation sequence and aligning by bit to obtain a weight matrix, removing slack bits in the weight matrix, allowing essential bits in each column of the weight matrix to fill the vacancies according to the computation sequence to obtain an intermediate matrix, removing null rows in the intermediate matrix, obtain a kneading matrix, wherein each row of the kneading matrix serves as a kneading weight; obtaining positional information of the activation corresponding to each bit of the kneading weight; divides the kneading weight by bit into multiple weight segments, processing summation of the weight segments and the corresponding activations according to the positional information, and sending a processing result to an adder tree to obtain an output feature map by means of executing shift-and-add on the processing result.
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公开(公告)号:US11580367B2
公开(公告)日:2023-02-14
申请号:US16079525
申请日:2016-08-09
Inventor: Zidong Du , Qi Guo , Tianshi Chen , Yunji Chen
Abstract: The present disclosure provides a neural network processing system that comprises a multi-core processing module composed of a plurality of core processing modules and for executing vector multiplication and addition operations in a neural network operation, an on-chip storage medium, an on-chip address index module, and an ALU module for executing a non-linear operation not completable by the multi-core processing module according to input data acquired from the multi-core processing module or the on-chip storage medium, wherein the plurality of core processing modules share an on-chip storage medium and an ALU module, or the plurality of core processing modules have an independent on-chip storage medium and an ALU module. The present disclosure improves an operating speed of the neural network processing system, such that performance of the neural network processing system is higher and more efficient.
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公开(公告)号:US10805233B2
公开(公告)日:2020-10-13
申请号:US15781686
申请日:2016-06-17
Inventor: Huiying Lan , Tao Luo , Shaoli Liu , Shijin Zhang , Yunji Chen
IPC: H04L12/911 , G06F15/173 , H04L12/44 , H04L12/755 , H04L12/933
Abstract: A communication structure comprises: a central node that is a communication data center of a network-on-chip and used for broadcasting or multicasting communication data to a plurality of leaf nodes; a plurality of leaf nodes that are communication data nodes of the network-on-chip and used for transmitting the communication data to the central node; and forwarder modules for connecting the central node with the plurality of leaf nodes and forwarding the communication data, wherein the plurality of leaf nodes are divided into N groups, each group having the same number of leaf nodes, the central node is individually in communication connection with each group of leaf nodes by means of the forwarder modules, the communication structure is a fractal-tree structure, the communication structure constituted by each group of leaf nodes has self-similarity, and the forwarder modules comprises a central forwarder module, leaf forwarder modules, and intermediate forwarder modules.
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公开(公告)号:US10416964B2
公开(公告)日:2019-09-17
申请号:US15773974
申请日:2016-06-17
Inventor: Zhen Li , Shaoli Liu , Shijin Zhang , Tao Luo , Cheng Qian , Yunji Chen , Tianshi Chen
Abstract: The present disclosure discloses an adder device, a data accumulation method and a data processing device. The adder device comprises: a first adder module provided with an adder tree unit, composed of a multi-stage adder array, and a first control unit, wherein the adder tree unit accumulates data by means of step-by-step accumulation based on a control signal of the first control unit; a second adder module comprising a two-input addition/subtraction operation unit and a second control unit, and used for performing an addition or subtraction operation on input data; a shift operation module for performing a left shift operation on output data of the first adder module; an AND operation module for performing an AND operation on output data of the shift operation module and output data of the second adder module; and a controller module.
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公开(公告)号:US20180321911A1
公开(公告)日:2018-11-08
申请号:US15773974
申请日:2016-06-17
Inventor: Zhen Li , Shaoli Liu , Shijin Zhang , Tao Lou , Cheng Qian , Yunji Chen , Tianshi Chen
CPC classification number: G06F7/50 , G06F7/501 , G06F7/509 , G06F2207/4824 , G06N3/063 , G06N3/08 , G06N5/003
Abstract: The present disclosure discloses an adder device, a data accumulation method and a data processing device. The adder device comprises: a first adder module provided with an adder tree unit, composed of a multi-stage adder array, and a first control unit, wherein the adder tree unit accumulates data by means of step-by-step accumulation based on a control signal of the first control unit; a second adder module comprising a two-input addition/subtraction operation unit and a second control unit, and used for performing an addition or subtraction operation on input data; a shift operation module for performing a left shift operation on output data of the first adder module; an AND operation module for performing an AND operation on output data of the shift operation module and output data of the second adder module; and a controller module.
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