公开(公告)号：US09304739B1

公开(公告)日：2016-04-05

申请号：US11609273

申请日：2006-12-11

Applicant: Norbert Juffa

Inventor： Norbert Juffa

IPC: G06F7/483 ,  G06T15/00

CPC classification number: G06F7/4833 ,  G06T15/005 ,  G06T2210/32

Abstract: Embodiments of the present invention set forth a technique for optimizing the performance and efficiency of complex, software-based computations, such as lighting computations. Data entering a graphics application programming interface (API) in a conventional arithmetic representation, such as floating-point or fixed-point, is converted to an internal logarithmic representation for greater computational efficiency. Lighting computations are then performed using logarithmic space arithmetic routines that, on average, execute more efficiently than similar routines performed in a native floating-point format. The lighting computation results, represented as logarithmic space numbers, are converted back to floating-point numbers before being transmitted to a graphics processing unit (GPU) for further processing. Because of efficiencies of logarithmic space arithmetic, performance improvements may be realized relative to prior art approaches to performing software-based floating-point operations.

Abstract translation: 本发明的实施例提出了一种用于优化复杂的基于软件的计算（诸如照明计算）的性能和效率的技术。 以常规算术表示形式（如浮点或定点）输入图形应用程序编程接口（API）的数据被转换为内部对数表示，以提高计算效率。 然后使用对数空间算术程序执行照明计算，平均来说，执行比以本机浮点格式执行的类似例程更有效。 表示为对数空格数的照明计算结果在传输到图形处理单元（GPU）以进一步处理之前被转换回浮点数。 由于对数空间算术的效率，相对于执行基于软件的浮点运算的现有技术方法，可以实现性能改进。

公开(公告)号：US08860741B1

公开(公告)日：2014-10-14

申请号：US11608436

申请日：2006-12-08

Applicant: Norbert Juffa ,  Stuart F. Oberman

Inventor： Norbert Juffa ,  Stuart F. Oberman

IPC: G09G5/36

CPC classification number: G09G5/36 ,  G06F9/50 ,  G06F12/0831 ,  G06F2212/302 ,  G09G5/363

Abstract: In contrast to a conventional computing system in which the graphics processor (graphics processing unit or GPU) is treated as a slave to one or several CPUs, systems and methods are provided that allow the GPU to be treated as a central processing unit (CPU) from the perspective of the operating system. The GPU can access a memory space shared by other CPUs in the computing system. Caches utilized by the GPU may be coherent with caches utilized by other CPUs in the computing system. The GPU may share execution of general-purpose computations with other CPUs in the computing system.

Abstract translation: 与将图形处理器（图形处理单元或GPU）视为一个或多个CPU的从属设备的常规计算系统相反，提供允许GPU被视为中央处理单元（CPU）的系统和方法， 从操作系统的角度。 GPU可以访问计算系统中其他CPU共享的内存空间。 GPU使用的高速缓存可能与计算系统中其他CPU所使用的高速缓存一致。 GPU可能与计算系统中的其他CPU共享通用计算的执行。

公开(公告)号：US07912889B1

公开(公告)日：2011-03-22

申请号：US11454680

申请日：2006-06-16

Applicant: Norbert Juffa ,  Radoslav Danilak

Inventor： Norbert Juffa ,  Radoslav Danilak

IPC: G06F7/52

CPC classification number: G06F17/16

Abstract: The present invention enables efficient matrix multiplication operations on parallel processing devices. One embodiment is a method for mapping CTAs to result matrix tiles for matrix multiplication operations. Another embodiment is a second method for mapping CTAs to result tiles. Yet other embodiments are methods for mapping the individual threads of a CTA to the elements of a tile for result tile computations, source tile copy operations, and source tile copy and transpose operations. The present invention advantageously enables result matrix elements to be computed on a tile-by-tile basis using multiple CTAs executing concurrently on different streaming multiprocessors, enables source tiles to be copied to local memory to reduce the number accesses from the global memory when computing a result tile, and enables coalesced read operations from the global memory as well as write operations to the local memory without bank conflicts.

Abstract translation: 本发明使得能够对并行处理装置进行有效的矩阵乘法运算。 一个实施例是用于将CTA映射到用于矩阵乘法运算的矩阵瓦片的方法。 另一个实施例是用于将CTA映射到结果瓦片的第二种方法。 其他实施例是用于将CTA的各个线程映射到块的元素以用于结果瓦片计算，源瓦片复制操作以及源瓦片复制和转置操作的方法。 本发明有利地使结果矩阵元素可以使用在不同的流式多处理器上同时执行的多个CTA来逐个瓦片地计算，使得能够将源瓦片复制到本地存储器，以减少当计算一个 结果图块，并且启用来自全局存储器的合并的读取操作以及对本地存储器的写入操作，而没有存储体冲突。

公开(公告)号：US07836118B1

公开(公告)日：2010-11-16

申请号：US11454499

申请日：2006-06-16

Applicant: Norbert Juffa ,  Radoslav Danilak

Inventor： Norbert Juffa ,  Radoslav Danilak

IPC: G06F17/16

CPC classification number: G06F17/16 ,  G06F9/3851 ,  G06F9/3885 ,  G06F9/3887

Abstract: The present invention enables efficient matrix multiplication operations on parallel processing devices. One embodiment is a method for mapping CTAs to result matrix tiles for matrix multiplication operations. Another embodiment is a second method for mapping CTAs to result tiles. Yet other embodiments are methods for mapping the individual threads of a CTA to the elements of a tile for result tile computations, source tile copy operations, and source tile copy and transpose operations. The present invention advantageously enables result matrix elements to be computed on a tile-by-tile basis using multiple CTAs executing concurrently on different streaming multiprocessors, enables source tiles to be copied to local memory to reduce the number accesses from the global memory when computing a result tile, and enables coalesced read operations from the global memory as well as write operations to the local memory without bank conflicts.

Abstract translation: 本发明使得能够对并行处理装置进行有效的矩阵乘法运算。 一个实施例是用于将CTA映射到用于矩阵乘法运算的矩阵瓦片的方法。 另一个实施例是用于将CTA映射到结果瓦片的第二种方法。 其他实施例是用于将CTA的各个线程映射到块的元素以用于结果瓦片计算，源瓦片复制操作以及源瓦片复制和转置操作的方法。 本发明有利地使结果矩阵元素可以使用在不同的流式多处理器上同时执行的多个CTA来逐个瓦片地计算，使得能够将源瓦片复制到本地存储器，以减少当计算一个 结果图块，并且启用来自全局存储器的合并的读取操作以及对本地存储器的写入操作，而没有存储体冲突。

公开(公告)号：US20070198412A1

公开(公告)日：2007-08-23

申请号：US11350137

申请日：2006-02-08

Applicant: Norbert Juffa

Inventor： Norbert Juffa

IPC: H04L9/00

CPC classification number: G06F21/72 ,  G06F9/30181 ,  G06F9/3879 ,  G06F2207/3824

Abstract: A graphics processing unit is programmed to carry out cryptographic processing so that fast, effective cryptographic processing solutions can be provided without incurring additional hardware costs. The graphics processing unit can efficiently carry out cryptographic processing because it has an architecture that is configured to handle a large number of parallel processes. The cryptographic processing carried out on the graphics processing unit can be further improved by configuring the graphics processing unit to be capable of both floating point and integer operations.

Abstract translation: 图形处理单元被编程为执行加密处理，使得可以提供快速有效的加密处理解决方案而不产生额外的硬件成本。 图形处理单元可以有效地执行加密处理，因为它具有被配置为处理大量并行进程的体系结构。 通过将图形处理单元配置为能够进行浮点运算和整数运算，可以进一步提高在图形处理单元上执行的加密处理。

公开(公告)号：US6105129A

公开(公告)日：2000-08-15

申请号：US25233

申请日：1998-02-18

Applicant: Stephan G. Meier ,  Norbert Juffa ,  Michael D. Achenbach ,  Frederick D. Weber

Inventor： Stephan G. Meier ,  Norbert Juffa ,  Michael D. Achenbach ,  Frederick D. Weber

IPC: G06F9/30 ,  G06F9/318 ,  G06F9/38 ,  G06F9/302

CPC classification number: G06F9/30181 ,  G06F9/30036 ,  G06F9/30112 ,  G06F9/30152 ,  G06F9/30185 ,  G06F9/384 ,  G06F9/3855 ,  G06F9/3861

Abstract: A microprocessor includes one or more registers which are architecturally defined to be used for at least two data formats. In one embodiment, the registers are the floating point registers defined in the x86 architecture, and the data formats are the floating point data format and the multimedia data format. The registers actually implemented by the microprocessor for the floating point registers use an internal format for floating point data. Part of the internal format is a classification field which classifies the floating point data in the extended precision defined by the x86 microprocessor architecture. Additionally, a classification field encoding is reserved for multimedia data. As the microprocessor begins execution of each multimedia instruction, the classification information of the source operands is examined to determine if the data is either in the multimedia class, or in a floating point class in which the significand portion of the register is the same as the corresponding significand in extended precision. If so, the multimedia instruction executes normally. If not, the multimedia instruction is faulted. Similarly, as the microprocessor begins execution of each floating point instruction, the classification information of the source operands is examined. If the data is classified as multimedia, the floating point instruction is faulted. A microcode routine is used to reformat the data stored in at least the source registers of the faulting instruction into a format useable by the faulting instruction. Subsequently, the faulting instruction is re-executed.

Abstract translation: 微处理器包括一个或多个寄存器，其被架构地定义为用于至少两种数据格式。 在一个实施例中，寄存器是在x86架构中定义的浮点寄存器，数据格式是浮点数据格式和多媒体数据格式。 微处理器为浮点寄存器实际实现的寄存器使用浮点数据的内部格式。 内部格式的一部分是分类字段，它以由x86微处理器架构定义的扩展精度对浮点数据进行分类。 此外，分类字段编码被保留用于多媒体数据。 当微处理器开始执行每个多媒体指令时，检查源操作数的分类信息以确定数据是在多媒体类中还是在浮点类中，其中寄存器的有效部分与 相应的显着性在扩展精度。 如果是这样，多媒体指令正常执行。 如果不是，则多媒体指令发生故障。 类似地，当微处理器开始执行每个浮点指令时，检查源操作数的分类信息。 如果数据被分类为多媒体，则浮点指令发生故障。 微码程序用于将存储在故障指令的至少源寄存器中的数据重新格式化为故障指令可使用的格式。 随后，重新执行故障指令。

公开(公告)号：US06029244A

公开(公告)日：2000-02-22

申请号：US948679

申请日：1997-10-10

Applicant: Stuart Oberman ,  Norbert Juffa

Inventor： Stuart Oberman ,  Norbert Juffa

IPC: G06F9/30 ,  G06F9/302 ,  G06F9/318 ,  G06F9/38 ,  G06F17/16 ,  G06F9/305

CPC classification number: G06F17/16 ,  G06F9/30014 ,  G06F9/30021 ,  G06F9/30036 ,  G06F9/30167 ,  G06F9/3017 ,  G06F9/3804 ,  G06F9/3885

Abstract: An execution unit is provided for executing a first instruction which includes an opcode field, a first operand field, and a second operand field. The execution unit includes a first input register for receiving a first operand specified by a value of the first operand field, and a second input register for receiving a second operand specified by a value of the second operand field. The execution unit further includes a comparator unit which is coupled to receive a value of the opcode field for the first instruction. The comparator unit is also coupled to receive the first and second operand values from the first and second input registers, respectively. The execution further includes a multiplexer which receives a plurality of inputs. These inputs include a first constant value, a second constant value, and the values of the first and second operand. If the decoded opcode value received by the comparator indicates that the first instruction is either a compare or extreme value function, the comparator conveys one or more control signals to the multiplexer for the purpose of selecting an output of the multiplexer as the result of the first instruction. If the first instruction is one of a plurality of extreme value instructions, the one or more control signals conveyed by the comparator unit select between the first operand and second operand to determine the result of the first instruction. If the first instruction is one of a plurality of compare instructions, the one or more control signals conveyed by the comparator unit select between the first and second constant value to determine the result of the first instruction. In another embodiment, a similar execution unit is provided which handles vector operands.