公开(公告)号：US06408265B1

公开(公告)日：2002-06-18

申请号：US09233529

申请日：1999-01-20

申请人： Richard T. Schultz ,  Kevin J. Gearhardt

发明人： Richard T. Schultz ,  Kevin J. Gearhardt

IPC分类号： G06F945

CPC分类号： G06F17/5022

摘要： A metastability risk simulation analysis device and method for identifying metastability risks of a design. The metastability risk simulation analysis device includes computer readable code which is configured to analyze simulation information relating to the design and determine whether the design presents a metastability risk. Desirably, the computer readable code is configured to determine whether two signals, such as a data signal and a clock signal of a synchronous element of the design, cross over each other thereby presenting a metastability risk, and is configured to generate a summary report identifying those synchronous elements of the design which present a metastability risk. Preferably, the computer readable code is configured to analyze simulation information relating to best case and worst case simulations of the design, and is configured to scan the simulation information to identify an edge of a clock signal and an edge of a data signal of the best case and worst case simulations and determine whether the signals cross each other.

摘要翻译： 一种用于识别设计的亚稳态风险的亚稳态风险模拟分析装置和方法。 亚稳态风险模拟分析装置包括计算机可读代码，其被配置为分析与设计有关的模拟信息，并确定设计是否呈现亚稳态风险。 期望地，计算机可读代码被配置为确定诸如设计的同步元件的数据信号和时钟信号的两个信号是否相互交叉从而呈现亚稳定性风险，并且被配置为生成识别 那些呈现亚稳态风险的设计的同步元件。 优选地，计算机可读代码被配置为分析与设计的最佳情况和最坏情况模拟相关的模拟信息，并且被配置为扫描模拟信息以识别时钟信号的边缘和最佳数据信号的边缘 情况和最坏情况模拟，并确定信号是否交叉。

公开(公告)号：US06346721B1

公开(公告)日：2002-02-12

申请号：US09804118

申请日：2001-03-12

申请人： Richard T. Schultz

发明人： Richard T. Schultz

IPC分类号： H01L2710

CPC分类号： H01L23/5286 ,  H01L2924/0002 ,  H01L2924/00

摘要： An integrated circuit includes a substrate of semiconductor material having a periphery and a geometric center, a plurality of circuits formed on the substrate, and a power bus grid electrically coupled to the plurality of circuits. The power bus grid is formed of a plurality of power bus straps having a strap density that progressively varies with distance from the geometric center toward the periphery.

摘要翻译： 集成电路包括具有周边和几何中心的半导体材料的衬底，形成在衬底上的多个电路，以及电耦合到多个电路的电力总线栅极。 电力总线栅格由多个电源母线带形成，带子密度随着几何中心向周边的距离而逐渐变化。

公开(公告)号：US06340905B1

公开(公告)日：2002-01-22

申请号：US09596677

申请日：2000-06-19

申请人： Richard T. Schultz

发明人： Richard T. Schultz

IPC分类号： G06F104

CPC分类号： G06F1/10

摘要： A clock tree deskew circuit dynamically minimizes skew in clock signals that synchronize operation of synchronized circuit components of an integrated circuit. The clock tree deskew circuit reduces the clock tree skew in repeated intervals over a period of time. The clock tree deskew circuit is then turned off to prevent unnecessary further adjustments to the clock signals, but can be turned back on when conditions change that alter the clock tree skew. The clock signals are paired together in a continuous loop, such that each clock signal is the first clock signal of the pair when paired with the next clock signal and is the second clock signal when paired with the one before it. The clock tree deskew circuit detects the absolute skew between each pair of the clock signals. The clock tree deskew circuit adjusts the first clock signal of each pair toward the second clock signal of the pair to reduce the skew between the two clock signals. After a predetermined number of adjustment cycles, the overall clock skew is minimized by repeated adjustments.

摘要翻译： 时钟树去偏置电路动态地最小化同步集成电路的同步电路组件的操作的时钟信号的偏移。 时钟树偏移电路在一段时间内以重复的间隔减少时钟树的偏斜。 然后关闭时钟树偏移电路，以防止对时钟信号进行不必要的进一步调整，但是当条件改变时可以重新启动时钟树偏移。 时钟信号以连续的环路配对在一起，使得当与下一个时钟信号配对时，每个时钟信号是该对的第一个时钟信号，并且当与之前的时钟信号配对时是第二个时钟信号。 时钟树偏移电路检测每对时钟信号之间的绝对偏差。 时钟树偏移电路调整每对的第一个时钟信号朝向该对的第二个时钟信号，以减少两个时钟信号之间的偏差。 在预定数量的调整周期之后，通过重复调整来最小化整个时钟偏移。

公开(公告)号：US5999029A

公开(公告)日：1999-12-07

申请号：US671862

申请日：1996-06-28

申请人： Hoang P. Nguyen ,  Richard T. Schultz

发明人： Hoang P. Nguyen ,  Richard T. Schultz

IPC分类号： H03K3/037

CPC分类号： H03K3/0375

摘要： A meta-hardened circuit that reduces the effects of metastability preferably includes a pulse generator coupled to receive a first clock signal and generate in response thereto a second clock signal and an enable signal. A buffer, preferably tri-state, is coupled to receive a first data signal and the enable signal and generate in response thereto a second data signal. A bi-stable device, such as a flip-flop, is coupled to receive the second clock signal and the second data signal. The pulse generator preferably includes a combining device and a delay device. The buffer preferably includes at least one tri-state inverter and a keeper circuit. A method to reduce the metastability effects preferably includes the step of generating a delay between a second data input signal and a second clock signal that is greater than a delay between a first data input signal and a first clock signal. The step of generating preferably occurs in one clock cycle. The method also preferably includes generating an enable pulse by generating a second clock signal in response to a first clock signal and combining the first and second clock signals to generate the enable signal, and generating a second data input signal in response to a first data input signal, where generating the second data input signal includes receiving an enable signal. The method preferably includes the step of generating an output signal in response to the second data input signal and the second clock signal, the output signal having a reduced metastable effect.

摘要翻译： 降低亚稳态影响的元硬化电路优选地包括脉冲发生器，其被耦合以接收第一时钟信号并响应于此产生第二时钟信号和使能信号。 耦合优选三态的缓冲器以接收第一数据信号和使能信号，并响应于此产生第二数据信号。 诸如触发器的双稳态器件被耦合以接收第二时钟信号和第二数据信号。 脉冲发生器优选地包括组合装置和延迟装置。 缓冲器优选地包括至少一个三态反相器和保持器电路。 降低亚稳效应的方法优选地包括产生第二数据输入信号和大于第一数据输入信号和第一时钟信号之间的延迟的第二时钟信号之间的延迟的步骤。 优选的发生步骤在一个时钟周期内发生。 该方法还优选地包括通过响应于第一时钟信号产生第二时钟信号并组合第一和第二时钟信号以产生使能信号来产生使能脉冲，以及响应于第一数据输入产生第二数据输入信号 信号，其中产生所述第二数据输入信号包括接收使能信号。 该方法优选地包括响应于第二数据输入信号和第二时钟信号产生输出信号的步骤，输出信号具有降低的亚稳效应。

公开(公告)号：US08563425B2

公开(公告)日：2013-10-22

申请号：US12475796

申请日：2009-06-01

申请人： Richard T. Schultz

发明人： Richard T. Schultz

IPC分类号： H01L21/4763

CPC分类号： H01L21/76897 ,  H01L21/76895 ,  H01L21/823437 ,  H01L21/823475

摘要： A semiconductor device fabrication process includes forming a gate of a transistor on a semiconductor substrate using a hard mask. The hard mask is selectively removed in one or more selected regions over the gate. The removal of the hard mask in the selected regions allows the gate to be connected to an upper metal layer through at least one insulating layer located substantially over the transistor. Conductive material is deposited in one or more trenches formed through the at least one insulating layer. The conductive material forms a local interconnect to the gate in at least one of the selected regions.

摘要翻译： 半导体器件制造工艺包括使用硬掩模在半导体衬底上形成晶体管的栅极。 在门上的一个或多个选定区域中选择性地去除硬掩模。 在所选择的区域中去除硬掩模允许栅极通过位于晶体管基本上的至少一个绝缘层连接到上金属层。 导电材料沉积在通过至少一个绝缘层形成的一个或多个沟槽中。 导电材料在所选择的区域中的至少一个中形成与栅极的局部互连。

公开(公告)号：US20120037996A1

公开(公告)日：2012-02-16

申请号：US13280848

申请日：2011-10-25

申请人： Richard T. Schultz ,  Donald R. Weiss

发明人： Richard T. Schultz ,  Donald R. Weiss

IPC分类号： H01L27/11

CPC分类号： H01L21/76895 ,  H01L21/845 ,  H01L27/11 ,  H01L27/1104 ,  H01L27/1211 ,  H01L2924/0002 ,  H01L2924/00

摘要： Improved SRAMs are formed with significantly reduced local interconnect to gate shorts, by a technique providing bidirectional, self-aligned local interconnects, employing a gate hard mask over portions of the gates not connected to the local interconnects. Embodiments include forming a gate hard mask over gates, forming bidirectional trenches overlying portions of the gate electrodes and active silicon regions, etching the hard mask layer to expose regions of the gate electrodes that are to connect to local interconnects, and filling the trenches with conductive material to form self-aligned local interconnects.

摘要翻译： 通过提供双向，自对准局部互连的技术，通过在未连接到局部互连的栅极的部分上采用栅极硬掩模，技术来形成改进的SRAM，从而显着减少与栅极短路的局部互连。 实施例包括在栅极上形成栅极硬掩模，形成覆盖栅极电极和有源硅区域的部分的双向沟槽，蚀刻硬掩模层以暴露栅极电极连接到局部互连的区域，以及用导电 材料以形成自对准局部互连。

公开(公告)号：US07960287B2

公开(公告)日：2011-06-14

申请号：US12891365

申请日：2010-09-27

申请人： Frank Scott Johnson ,  Richard T. Schultz

发明人： Frank Scott Johnson ,  Richard T. Schultz

IPC分类号： H01L21/311

CPC分类号： H01L21/823431 ,  H01L29/66795 ,  H01L29/66818

摘要： Methods for fabricating FinFET structures having gate structures of different gate widths are provided. The methods include the formation of sidewall spacers of different thicknesses to define gate structures of the FinFET structures with different gate widths. The width of a sidewall spacer is defined by the height of the structure about which the sidewall spacer is formed, the thickness of the sidewall spacer material layer from which the spacer is formed, and the etch parameters used to etch the sidewall spacer material layer. By forming structures of varying height, forming the sidewall spacer material layer of varying thickness, or a combination of these, sidewall spacers of varying width can be fabricated and subsequently used as an etch mask so that gate structures of varying widths can be formed simultaneously.

摘要翻译： 提供了制造具有不同栅极宽度的栅极结构的FinFET结构的方法。 这些方法包括形成不同厚度的侧壁间隔物，以限定具有不同栅极宽度的FinFET结构的栅极结构。 侧壁间隔物的宽度由形成侧壁间隔物的结构的高度，形成间隔物的侧壁间隔材料层的厚度和用于蚀刻侧壁间隔物材料层的蚀刻参数限定。 通过形成不同高度的结构，形成不同厚度的侧壁间隔物材料层或这些的组合，可以制造不同宽度的侧壁间隔物，并随后用作蚀刻掩模，从而可以同时形成不同宽度的栅极结构。

公开(公告)号：US20110014791A1

公开(公告)日：2011-01-20

申请号：US12891365

申请日：2010-09-27

申请人： Frank S. JOHNSON ,  Richard T. SCHULTZ

发明人： Frank S. JOHNSON ,  Richard T. SCHULTZ

IPC分类号： H01L21/311

CPC分类号： H01L21/823431 ,  H01L29/66795 ,  H01L29/66818

摘要： Methods for fabricating FinFET structures having gate structures of different gate widths are provided. The methods include the formation of sidewall spacers of different thicknesses to define gate structures of the FinFET structures with different gate widths. The width of a sidewall spacer is defined by the height of the structure about which the sidewall spacer is formed, the thickness of the sidewall spacer material layer from which the spacer is formed, and the etch parameters used to etch the sidewall spacer material layer. By forming structures of varying height, forming the sidewall spacer material layer of varying thickness, or a combination of these, sidewall spacers of varying width can be fabricated and subsequently used as an etch mask so that gate structures of varying widths can be formed simultaneously.

摘要翻译： 提供了制造具有不同栅极宽度的栅极结构的FinFET结构的方法。 这些方法包括形成不同厚度的侧壁间隔物，以限定具有不同栅极宽度的FinFET结构的栅极结构。 侧壁间隔物的宽度由形成侧壁间隔物的结构的高度，形成间隔物的侧壁间隔材料层的厚度和用于蚀刻侧壁间隔物材料层的蚀刻参数限定。 通过形成不同高度的结构，形成不同厚度的侧壁间隔物材料层或这些的组合，可以制造不同宽度的侧壁间隔物，并随后用作蚀刻掩模，从而可以同时形成不同宽度的栅极结构。

公开(公告)号：US07424690B2

公开(公告)日：2008-09-09

申请号：US11005690

申请日：2004-12-07

申请人： Richard T Schultz ,  Robert Waldron ,  Norman Mause ,  Larry Greenhouse

发明人： Richard T Schultz ,  Robert Waldron ,  Norman Mause ,  Larry Greenhouse

IPC分类号： G06F17/50

CPC分类号： G06F17/5036

摘要： A system and method for designing a complex electronic circuit by simulating blocks of the circuit using various simulators to produce a net list, designing the physical layout of the circuit using a layout tool that produces a layout verses schematic reference file, mapping the reference file to the net list to create a mapping file, and analyzing the mapping file to verify that the layout meets various criteria. Each block may be verified using simulation tools that are appropriate for that piece of the overall circuit, and using conditions that may maximize the strain on the circuit. The results from the simulations are compared to the physical layout to determine if the physical layout is able to properly conduct the electrical signals.

摘要翻译： 一种用于通过使用各种模拟器模拟电路块以产生网络列表来设计复杂电子电路的系统和方法，使用布局工具来设计电路的物理布局，该布局工具产生与示意图参考文件的布局，将参考文件映射到 创建映射文件的网络列表，并分析映射文件以验证布局符合各种标准。 可以使用适合于整个电路的该片的仿真工具来验证每个块，并且使用可以使电路上的应变最大化的条件。 将仿真的结果与物理布局进行比较，以确定物理布局是否能够正确地传导电信号。

公开(公告)号：US06653726B1

公开(公告)日：2003-11-25

申请号：US09948190

申请日：2001-09-07

申请人： Richard T. Schultz ,  Roger D. Weir

发明人： Richard T. Schultz ,  Roger D. Weir

IPC分类号： H01L3252

CPC分类号： H01L23/5286 ,  H01L2924/0002 ,  H01L2924/00

摘要： The subject matter described herein involves a wire bonded integrated circuit (IC) that includes a power distribution grid, or power redistribution bus, within a single layer, e.g. the topmost metallization layer, of the IC chip. Electrical conductors in the power distribution grid are generally L-shaped. Thus, the electrical conductors are arranged generally in symmetrical quadrants within which the electrical conductors extend from one side edge of the IC chip to a generally right-angled corner and then to a second side edge that is adjacent to the first side edge.

摘要翻译： 本文所述的主题涉及包括在单层内的配电网格或功率再分配总线的引线键合集成电路（IC），例如。 IC芯片的最顶层金属化层。 配电网中的电气导体通常为L形。 因此，电导体大致布置在对称象限中，电导体从IC芯片的一个侧边缘延伸到大致直角的角部，然后延伸到与第一侧边缘相邻的第二侧边缘。