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31.发明申请公开(公告)号：US20210240863A1
公开(公告)日：2021-08-05
申请号：US17161544
申请日：2021-01-28
Inventor： Gilles PELISSIER , Nicolas ANQUET , Delphine LE-GOASCOZ
Abstract: A unique hardware key is recorded a secure hardware environment. A first logic circuit of the secure hardware environment is configured to generate a unique derived key from said unique hardware key and at least one piece of information. The at least one piece of information relates to one or more of an execution context and a use of a secret key. The secure hardware environment further includes a first encryption device that performs a symmetric encryption of the secret key using the unique derived key. This symmetric encryption generates an encrypted secret key for use outside of the secure hardware environment.
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公开(公告)号：US10971925B2
公开(公告)日：2021-04-06
申请号：US16026503
申请日：2018-07-03
Applicant: STMicroelectronics (Alps) SAS
Inventor： Frederic Lebon , Laurent Chevalier
Abstract: An electronic circuit includes a switch coupled between an input terminal intended to receive a first voltage and an output terminal coupled to a decoupling capacitor and intended to also be coupled to a load. A comparison stage is configured to compare the first voltage and a second voltage that is present at the output terminal. A first adjustment stage is configured to limit a positive inrush current flowing between the input terminal and the output terminal and a second adjustment stage is configured to limit a negative inrush current flowing between the output terminal and the input terminal. A control circuit is configured to activate either the first adjustment stage or the second adjustment stage as a function of a result of the comparison.
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公开(公告)号：US10917087B2
公开(公告)日：2021-02-09
申请号：US16719053
申请日：2019-12-18
Inventor： Vanni Poletto , David F. Swanson , Giovanni Luca Torrisi , Laurent Chevalier
IPC: H03K17/687 , G01R19/165 , G05B11/42 , G05F1/618 , G05F1/56 , H02J7/34
Abstract: A circuit for controlling a first plurality of transistors connected in parallel and a second plurality of transistors connected in parallel, includes: a first plurality of stages, a respective one of the first plurality of stages being configured to supply a first control signal to a respective one of the first plurality of transistors; and a second plurality of stages, a respective one of the second plurality of stages being configured to supply a second control signal to a respective one of the second plurality of transistors. An output current of the respective one of the first plurality of stages is regulated based on a difference between a first value representative of a sum of output currents of each stage of the first plurality of stages and a second value representative of a sum of set points assigned to the first plurality of stages.
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公开(公告)号：US20210006215A1
公开(公告)日：2021-01-07
申请号：US16915766
申请日：2020-06-29
Applicant: STMicroelectronics SA , STMicroelectronics (Alps) SAS , STMicroelectronics razvoj polprevodnikov d.o.o.
Inventor： Kosta Kovacic , Christophe Grundrich , Bruno LEDUC , Anton Stern
Abstract: A method for controlling a signal envelope shape of modulation pulses in a driver of a wireless transmitter includes supplying a first voltage to the driver during a non-modulated state, supplying a second voltage configurable by a configurable modulation index value to the driver during a modulated state, switching between the non-modulated state and the modulated state comprising setting the modulation index value to configure the second voltage level at the same level as the first voltage and then switching between supplying the first voltage to the driver and supplying the second voltage to the driver, and filtering to a limited bandwidth the variations of the second voltage resulting from configuring the modulation index value.
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35.发明授权公开(公告)号：US10832780B2
公开(公告)日：2020-11-10
申请号：US16432369
申请日：2019-06-05
Inventor： Leonardo Valencia Rissetto , Elise Le Roux , Christophe Forel
Abstract: A method can be used for programming a group of memory cells of a non-volatile memory device in a programming window that has a duration longer than a programming duration of a memory cell. The programming window is subdivided into a number of time intervals. A programming profile that was determined by simulation while taking into account a reference criterion is retrieved. The programming profile includes, for each time interval, a maximum number of memory cells that can be triggered for programming within each time interval. The memory device is programmed in the programming window, interval-wise, using the programming profile.
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Patent Agency Ranking
公开(公告)号：US10522899B2
公开(公告)日：2019-12-31
申请号：US16017611
申请日：2018-06-25
Inventor： David Auchere , Laurent Marechal , Yvon Imbs , Laurent Schwarz
IPC: H01Q1/22 , H01L23/31 , H01L21/56 , H01L23/66 , H01L21/3105 , H01L21/48 , H01L23/498
Abstract: An electronic device includes a support plate having a mounting face and an electrical connection network. An integrated circuit chip is mounted on the mounting face and linked to the electrical connection network. An encapsulation block embeds the integrated circuit chip. An additional element made of an electrically conductive material is at least partly embedded within the encapsulation block. The additional conductive element has a main portion extending parallel to the support plate and has a secondary portion that is linked electrically to the integrated circuit chip. An opening is formed in the encapsulation block, and the secondary portion extends into that opening to make the electrical link. The additional conductive element may be an antenna.
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公开(公告)号：US10520554B2
公开(公告)日：2019-12-31
申请号：US16269331
申请日：2019-02-06
Inventor： Vratislav Michal , Michel Ayraud
Abstract: A circuit includes an amplifier having a first power terminal configured to be coupled to a supply voltage and a second power terminal configured to be coupled to a reference potential. The circuit further includes a first impedance element coupled between a first input terminal of the amplifier and a first output terminal of the amplifier. The circuit additionally includes a second impedance element coupled between the first input terminal and the reference potential. The amplifier is configured to output a first voltage at a second output terminal of the amplifier in response to the supply voltage being greater than an output voltage at the first output terminal of the amplifier. The amplifier is further configured to output a second voltage at the second output terminal of the amplifier in response to the supply voltage being less than the output voltage at the first output terminal of the amplifier.
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公开(公告)号：US20190319538A1
公开(公告)日：2019-10-17
申请号：US16385284
申请日：2019-04-16
Applicant: STMicroelectronics S.r.l. , STMicroelectronics (Alps) SAS
Inventor： Francois Druilhe , Patrik Arno , Alessandro Inglese , Michele Alessandro Carrano
Abstract: A power supply system includes a voltage application source, and a switched mode power supply having an output coupled to the voltage application source through a first path and through a second path different from the first path. A first node is coupled to the output of the switched mode power supply, the switched mode power supply being configured to couple the first node to the voltage application source through the first path in a first operating mode and through the second path in a different second operating mode. A digital regulator is coupled to the first node. A digital circuit is coupled to an output of the digital regulator. An analog regulator is coupled to the first node and an analog circuit coupled to an output of the analog regulator.
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公开(公告)号：US20190267991A1
公开(公告)日：2019-08-29
申请号：US16274844
申请日：2019-02-13
Inventor： Vanni Poletto , David F. Swanson , Giovanni Luca Torrisi , Laurent Chevalier
IPC: H03K17/687 , G05B11/42 , G01R19/165
Abstract: A circuit for controlling a first plurality of transistors connected in parallel and a second plurality of transistors connected in parallel, includes: a first plurality of stages, a respective one of the first plurality of stages being configured to supply a first control signal to a respective one of the first plurality of transistors; and a second plurality of stages, a respective one of the second plurality of stages being configured to supply a second control signal to a respective one of the second plurality of transistors. An output current of the respective one of the first plurality of stages is regulated based on a difference between a first value representative of a sum of output currents of each stage of the first plurality of stages and a second value representative of a sum of set points assigned to the first plurality of stages.
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公开(公告)号：US20190235551A1
公开(公告)日：2019-08-01
申请号：US16381541
申请日：2019-04-11
Applicant: STMicroelectronics (Alps) SAS
Inventor： Alexandre Pons
CPC classification number: G05F1/59 , G05F1/56 , G05F1/569 , H01R24/60 , H01R2107/00 , H02J7/022 , H02J7/06 , H02J2007/10 , H03F3/45071 , H03F2203/45521 , H03F2203/45641
Abstract: A low dropout voltage regulator unit includes an error amplifier and a power stage having an output terminal that is looped back onto the error amplifier and is capable of delivering an output current to a load. The unit includes multiple main supply inputs that are intended to potentially receive, respectively, multiple different supply voltages. The power stage includes multiple power paths that are connected, respectively, between the main supply inputs and the output terminal, are individually selectable and each comprise an output transistor. The unit also includes a selector circuit connected to the main supply inputs and configured to select one of the power paths according to a selection criterion. The error amplifier includes an output stage configured to selectively control the output transistor of the selected power path.
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