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    ACTIVE CYCYLE CONTROL CIRCUIT FOR SEMICONDUCTOR MEMORY APPARATUS
    33.
    发明申请
    ACTIVE CYCYLE CONTROL CIRCUIT FOR SEMICONDUCTOR MEMORY APPARATUS 有权
    用于半导体存储器的主动循环控制电路

    公开(公告)号：US20090185440A1

    公开(公告)日：2009-07-23

    申请号：US12411613

    申请日：2009-03-26

    Applicant: SANG KWON LEE

    Inventor： SANG KWON LEE

    IPC: G11C7/00

    CPC classification number: G11C11/406 ,  G11C7/1063 ,  G11C2211/4067

    Abstract: An active cycle control circuit for a semiconductor memory apparatus is configured to precharge a word line corresponding to a read cycle, and activate a word line corresponding to a refresh request signal in response to the refresh request signal generated during the read cycle.

    Abstract translation: 半导体存储装置的有源周期控制电路被配置为对与读周期相对应的字线进行预充电，并且响应于在读周期期间产生的刷新请求信号，激活与刷新请求信号对应的字线。

    Active cycle control circuit and method for semiconductor memory apparatus
    34.
    发明授权
    Active cycle control circuit and method for semiconductor memory apparatus 有权
    半导体存储装置的主动周期控制电路及方法

    公开(公告)号：US07515495B2

    公开(公告)日：2009-04-07

    申请号：US11647435

    申请日：2006-12-29

    Applicant: Sang-Kwon Lee

    Inventor： Sang-Kwon Lee

    IPC: G11C7/00

    CPC classification number: G11C11/406 ,  G11C7/1063 ,  G11C2211/4067

    Abstract: An active cycle control circuit includes a refresh active control signal generation unit that generates a refresh active control signal at the same cycle as a refresh request signal at a timing earlier than the refresh request signal, a refresh standby signal output unit that outputs a refresh standby signal according to a refresh active signal and the refresh request signal, and an active control unit that outputs a row active signal for performing a read cycle according to a read command and outputs the refresh active signal according to the refresh active control signal and the refresh standby signal within the read cycle.

    Abstract translation: 一个主动周期控制电路包括一个刷新主动控制信号产生单元，该刷新主动控制信号产生单元在比刷新请求信号更早的时间以与刷新请求信号相同的周期产生刷新主动控制信号;刷新待机信号输出单元，其输出刷新待机 根据刷新活动信号和刷新请求信号的信号，以及根据读取命令输出用于执行读取周期的行活动信号的有源控制单元，并且根据刷新主动控制信号和刷新输出刷新活动信号 待机信号在读周期内。

    Address synchronous circuit capable of reducing current consumption in dram
    35.
    发明申请
    Address synchronous circuit capable of reducing current consumption in dram 有权
    地址同步电路，能够降低电流消耗

    公开(公告)号：US20090003122A1

    公开(公告)日：2009-01-01

    申请号：US12005707

    申请日：2007-12-28

    Applicant: Sang Kwon Lee

    Inventor： Sang Kwon Lee

    IPC: G11C8/00

    CPC classification number: G11C8/18 ,  G11C7/1072 ,  G11C8/06 ,  G11C11/4076 ,  G11C11/4082

    Abstract: An address synchronous circuit comprises an address control signal generating unit for generating a control signal in response to operation mode signals of a semiconductor memory and an internal clock signal, and an address synchronous unit for controlling output of an address which is buffered in accordance with a clock enable signal, in response to the control signal.

    Abstract translation: 地址同步电路包括地址控制信号产生单元，用于响应于半导体存储器和内部时钟信号的操作模式信号产生控制信号，以及地址同步单元，用于控制根据 时钟使能信号，响应控制信号。

    Circuit and method for detecting synchronous mode in a semiconductor memory apparatus
    36.
    发明授权
    Circuit and method for detecting synchronous mode in a semiconductor memory apparatus 失效
    用于在半导体存储装置中检测同步模式的电路和方法

    公开(公告)号：US07450464B2

    公开(公告)日：2008-11-11

    申请号：US11641044

    申请日：2006-12-19

    Applicant: Sang-Kwon Lee

    Inventor： Sang-Kwon Lee

    IPC: G11C11/00

    CPC classification number: G11C7/1045 ,  G11C7/22

    Abstract: A circuit for detecting synchronous mode in a semiconductor memory apparatus includes a control unit that controls the driving of a clock according to whether or not a valid address signal is enabled. A driving unit drives the clock according to the control of the control unit. A latch unit latches the clock driven by the driving unit and outputs a synchronous mode signal.

    Abstract translation: 一种用于在半导体存储装置中检测同步模式的电路包括：控制单元，其根据是否启用有效的地址信号来控制时钟的驱动。 驱动单元根据控制单元的控制驱动时钟。 锁存单元锁存由驱动单元驱动的时钟并输出同步模式信号。

    Address buffer and method for buffering address in semiconductor memory apparatus
    37.
    发明授权
    Address buffer and method for buffering address in semiconductor memory apparatus 有权
    用于在半导体存储装置中缓存地址的地址缓冲器和方法

    公开(公告)号：US07450463B2

    公开(公告)日：2008-11-11

    申请号：US11641032

    申请日：2006-12-19

    Applicant: Sang-Kwon Lee

    Inventor： Sang-Kwon Lee

    IPC: G11C11/00

    CPC classification number: G11C8/06 ,  G11C8/18

    Abstract: An address buffer in a semiconductor memory apparatus includes: an address input unit that generates a first latch input address from a buffering enable signal and an input address. A clock synchronizing unit generates a second latch input address from the first latch input address and a clock. A synchronous address latch unit generates a synchronous output address from a command pulse signal and the second latch input address. A synchronous mode detecting unit determines whether a mode is a synchronous mode or not from a valid address signal and the clock to generate a synchronous mode signal. An asynchronous address latch unit generates an asynchronous output address from the synchronous mode signal, an address strobing signal, and the second latch input address.

    Abstract translation: 半导体存储装置中的地址缓冲器包括：地址输入单元，其从缓冲使能信号和输入地址生成第一锁存器输入地址。 时钟同步单元从第一锁存器输入地址和时钟产生第二锁存器输入地址。 同步地址锁存单元根据命令脉冲信号和第二锁存器输入地址产生同步输出地址。 同步模式检测单元从有效地址信号和时钟确定模式是否是同步模式，以产生同步模式信号。 异步地址锁存单元从同步模式信号，地址选通信号和第二锁存器输入地址产生异步输出地址。

    Memory device for reducing leakage current
    38.
    发明授权
    Memory device for reducing leakage current 有权
    用于减少漏电流的存储器件

    公开(公告)号：US07193926B2

    公开(公告)日：2007-03-20

    申请号：US11158492

    申请日：2005-06-22

    Applicant: Sang Il Park ,  Sang Kwon Lee

    Inventor： Sang Il Park ,  Sang Kwon Lee

    IPC: G11C8/00

    CPC classification number: G11C29/83

    Abstract: Disclosed is a memory device for reducing leakage current generated by a bridge between a word line and a bit line when the memory device is in a waiting mode. The memory device includes: N memory cell blocks each of which includes plurality of memory cell blocks, wherein N represents a natural number; (N+1) sense amp blocks corresponding to the N memory cell blocks; 2N switching blocks connecting the N memory cell blocks to the (N+1) sense amp blocks, respectively; and N controllers for controlling the 2N switching blocks, respectively, wherein the N controllers turn off the 2N switching blocks when the memory device is in a waiting mode, and the N controllers selectively turn on the 2N switching blocks when the memory device is in an operation mode.

    Abstract translation: 公开了一种用于在存储器件处于等待模式时减少由字线和位线之间的桥产生的泄漏电流的存储器件。 存储器件包括：N个存储单元块，每个存储单元块包括多个存储单元块，其中N代表自然数; （N + 1）个对应于所述N个存储单元块的读出放大器块; 2N个切换块，分别将N个存储单元块连接到（N + 1）个读出放大器块; 和N个控制器，用于分别控制2N个切换块，其中N个控制器在存储器件处于等待模式时关闭2N个切换块，并且当存储器件处于等待模式时，N个控制器选择性地接通2N个切换块 操作模式。

    Test vehicle grid array package
    39.
    发明授权
    Test vehicle grid array package 有权
    测试车辆网格阵列包装

    公开(公告)号：US07193315B2

    公开(公告)日：2007-03-20

    申请号：US10618955

    申请日：2003-07-14

    Applicant: Chae Kyu Jang ,  Sang Kwon Lee

    Inventor： Chae Kyu Jang ,  Sang Kwon Lee

    IPC: H01L23/12 ,  H01L23/48 ,  H01L23/52

    CPC classification number: H01L22/34 ,  H01L24/45 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2924/01079 ,  H01L2924/15311 ,  H01L2924/16195 ,  H01L2924/30107 ,  H01L2924/00014 ,  H01L2924/00

    Abstract: A TV-BGA package comprises: a PCB having bonding fingers; an adhesive material being coated on an edge of the PCB; a sealing post being adhered on the adhesive material; a semiconductor testing chip having a plurality of bonding pads adhered on the PCB; a plurality of metal wires separately connecting bonding pads of the PCB to the bonding fingers of the PCB; a sealing cap adhered on a sealing post for sealing the semiconductor chip; and a plurality of solder balls adhered to a lower side of the PCB. An extrusion is formed at a upper end of the sealing post, and the sealing cap is adhered on the extrusion of the sealing post. Further, the sealing cap is adhered on the extrusion of the sealing post by a low temperature thermoplastic tape or a material similar to low temperature thermoplastic tape. In the TV-BGA package, a sealing post is adhered on the adhesive material coated on an edge of the PCB, and then a sealing cap is capped on the sealing post, so that a test vehicle is manufactured. Therefore, the TV-BGA package can be easily manufactured and is suitable to test high density and speed elements.

    Abstract translation: TV-BGA封装包括：具有接合指的PCB; 涂覆在PCB的边缘上的粘合剂材料; 密封柱粘附在粘合剂材料上; 半导体测试芯片，其具有粘附在PCB上的多个焊盘; 多个金属线将PCB的接合焊盘分别连接到PCB的接合指; 密封帽，其粘附在密封柱上以密封半导体芯片; 以及粘附到PCB的下侧的多个焊球。 在密封柱的上端形成挤压件，密封盖粘接在密封柱的挤压件上。 此外，密封盖通过低温热塑性带或类似于低温热塑性带的材料粘附在密封柱的挤出上。 在TV-BGA封装中，将密封柱粘附在涂覆在PCB的边缘上的粘合剂材料上，然后将密封帽盖在密封柱上，从而制造测试车辆。 因此，TV-BGA封装可以容易地制造，并且适合于测试高密度和速度元件。

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