中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

120 records (took 0.032 seconds)

    A4-SIZE SCANNER HAVING FUNCTION OF SCANNING A3 DOCUMENT AND SCANNING METHOD THEREOF
    32.
    发明申请
    A4-SIZE SCANNER HAVING FUNCTION OF SCANNING A3 DOCUMENT AND SCANNING METHOD THEREOF 有权
    具有扫描功能的A4尺寸扫描仪A3文件及其扫描方法

    公开(公告)号：US20100296130A1

    公开(公告)日：2010-11-25

    申请号：US12567812

    申请日：2009-09-28

    Applicant: Byoung Bag LEE ,  Nam Ik CHO ,  Sung Hoon LEE

    Inventor： Byoung Bag LEE ,  Nam Ik CHO ,  Sung Hoon LEE

    IPC: H04N1/387

    CPC classification number: H04N1/3876 ,  H04N1/00567 ,  H04N1/0057 ,  H04N1/00602 ,  H04N1/0405 ,  H04N1/193

    Abstract: An A4-size scanner capable of scanning an A3 document. The A4-size scanner includes a scanning part, a transferring roller member that is disposed at an upper side of the flat glass to be orthogonal to a length direction of the automatic document feeding unit and the scanning sensor so that the document having a double size of a scanning capacity of the scanning sensor and introduced onto the flat glass in the length direction of the automatic document feeding unit and the scanning sensor is transferred to a transferring roller, and a transferring roller member driving motor that is connected with the transferring roller which dividedly scans the document having a larger size than the scanning capacity of the scanning sensor; and an image processing part which performs an image processing for composing two images which are dividedly scanned through the scanning part.

    Abstract translation: 可扫描A3文档的A4尺寸扫描仪。 A4尺寸扫描仪包括扫描部分，设置在平板玻璃的上侧以与自动原稿进给单元的长度方向垂直的传送滚筒部件和扫描传感器，使得具有双重尺寸的文档 扫描传感器的扫描能力并沿着自动原稿供给单元的长度方向被引入到平板玻璃上，扫描传感器被传送到转印辊，以及与转印辊连接的转印辊构件驱动电机， 分别扫描具有比扫描传感器的扫描容量大的尺寸的文档; 以及图像处理部，其执行用于构成通过扫描部分分割扫描的两个图像的图像处理。

    Display apparatuses and methods of operating the same
    33.
    发明申请
    Display apparatuses and methods of operating the same 有权
    显示装置及其操作方法

    公开(公告)号：US20100149138A1

    公开(公告)日：2010-06-17

    申请号：US12458312

    申请日：2009-07-08

    Applicant: Sung-hoon Lee ,  Do-hyun Kim ,  Sang-wook Kim ,  Chang-jung Kim

    Inventor： Sung-hoon Lee ,  Do-hyun Kim ,  Sang-wook Kim ,  Chang-jung Kim

    IPC: G09G5/00 ,  G09G3/36

    CPC classification number: G02F1/1368 ,  G09G3/3648 ,  G09G2330/027

    Abstract: Provided are display apparatuses and methods of operating the same. In a display apparatus, a display image may be continuously held for longer than about 10 msec after the power of the display panel is turned off. The display apparatus may indicate a liquid crystal display (LCD) apparatus including an oxide thin film transistor (TFT). Off leakage current of the oxide TFT may be less than about 10−14 A.

    Abstract translation: 提供了显示装置及其操作方法。 在显示装置中，在显示面板的电源关闭之后，显示图像可以连续保持超过约10毫秒。 显示装置可以指示包括氧化物薄膜晶体管（TFT）的液晶显示器（LCD）装置。 氧化物TFT的漏电流可以小于约10-14A。

    Method of forming gate electrode pattern in semiconductor device
    34.
    发明授权
    Method of forming gate electrode pattern in semiconductor device 失效
    在半导体器件中形成栅电极图案的方法

    公开(公告)号：US07544564B2

    公开(公告)日：2009-06-09

    申请号：US11297885

    申请日：2005-12-09

    Applicant: Sung Hoon Lee

    Inventor： Sung Hoon Lee

    IPC: H01L21/336

    CPC classification number: H01L27/115 ,  H01L27/11521 ,  H01L27/11524

    Abstract: A method for forming a semiconductor device includes forming a gate dielectric layer over a substrate; forming a first conductive layer over the substrate; forming a dielectric layer over the first conductive layer; forming a second conductive layer over the dielectric layer; forming a sacrificial layer over the second conductive layer; patterning the sacrificial and other layers to form a plurality of gate electrode patterns; forming a buried oxide layer over and between the gate electrode patterns; and removing the sacrificial layer to form a plurality of trenches surrounded by the buried oxide layer. A metal layer is formed within the trench to form a plurality of metal gate structures, the metal layer contacting the second conductive layer that is exposed by the removal of the sacrificial layer.

    Abstract translation: 一种用于形成半导体器件的方法包括在衬底上形成栅极电介质层; 在所述衬底上形成第一导电层; 在所述第一导电层上形成介电层; 在介电层上形成第二导电层; 在所述第二导电层上形成牺牲层; 图案化牺牲层和其它层以形成多个栅电极图案; 在栅极电极图案之上和之间形成掩埋氧化物层; 并且去除所述牺牲层以形成被所述掩埋氧化物层包围的多个沟槽。 在沟槽内形成金属层以形成多个金属栅极结构，金属层与通过去除牺牲层而暴露的第二导电层接触。

    Method of Forming Gate of Semiconductor Device
    35.
    发明申请
    Method of Forming Gate of Semiconductor Device 有权
    半导体器件栅极形成方法

    公开(公告)号：US20090111266A1

    公开(公告)日：2009-04-30

    申请号：US12163420

    申请日：2008-06-27

    Applicant: Sung Hoon Lee

    Inventor： Sung Hoon Lee

    IPC: H01L21/302

    CPC classification number: H01L21/28273

    Abstract: A method of forming a gate of a semiconductor device comprising providing a semiconductor substrate over which a gate insulating layer, a first conductive layer, a dielectric layer, and a second conductive layer are sequentially formed, the semiconductor substrate defining gate line regions; removing he second conductive layer between gate line regions; removing the dielectric layer so that a top surface of the first conductive layer between the gate line regions is exposed; performing a first etch process in order to lower a height of the first conductive layer between the gate line region; removing he dielectric layer between the gate line regions; and, performing a second etch process in order to remove the first conductive layer between the gate line regions.

    Abstract translation: 一种形成半导体器件的栅极的方法，包括提供半导体衬底，栅极绝缘层，第一导电层，电介质层和第二导电层依次形成在其上，所述半导体衬底限定栅极线区域; 去除栅极线区域之间的第二导电层; 去除所述电介质层，使得所述栅极线区域之间的所述第一导电层的顶表面露出; 执行第一蚀刻工艺以便降低栅极线区域之间的第一导电层的高度; 去除栅极线区域之间的介电层; 以及执行第二蚀刻工艺以便去除栅极线区域之间的第一导电层。

    P-type semiconductor carbon nanotube using halogen element and fullerene or alkali element
    36.
    发明授权
    P-type semiconductor carbon nanotube using halogen element and fullerene or alkali element 有权
    使用卤素元素和富勒烯或碱元素的P型半导体碳纳米管

    公开(公告)号：US07501650B2

    公开(公告)日：2009-03-10

    申请号：US11202185

    申请日：2005-08-12

    Applicant: Noe-jung Park ,  Sung-hoon Lee

    Inventor： Noe-jung Park ,  Sung-hoon Lee

    IPC: H01L29/10

    CPC classification number: B82Y30/00 ,  C01B32/174 ,  D01F11/121 ,  Y10S977/734 ,  Y10S977/742

    Abstract: A p-type semiconductor carbon nanotube and a method of manufacturing the same are provided. The p-type semiconductor carbon nanotube includes a carbon nanotube; and a halogen element that is attached to an inner wall of the carbon nanotube and accepts electrons from the carbon nanotube to achieve p-type doping of the carbon nanotube. The p-type semiconductor carbon nanotube is stable at high temperatures and can maintain intrinsic good electrical conductivity of the carbon nanotube. The p-type semiconductor carbon nanotube can be relatively easily obtained using a conventional method of manufacturing a carbon nanotube, thereby significantly broadening the range of application of the carbon nanotube to electronic devices.

    Abstract translation: 提供了p型半导体碳纳米管及其制造方法。 p型半导体碳纳米管包括碳纳米管; 以及附着在碳纳米管的内壁上并从碳纳米管接收电子以实现碳纳米管的p型掺杂的卤素元素。 p型半导体碳纳米管在高温下是稳定的并且可以保持碳纳米管的本征良好的导电性。 可以使用常规的碳纳米管制造方法相对容易地获得p型半导体碳纳米管，从而显着拓宽碳纳米管应用于电子器件的范围。

    METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE
    37.
    发明申请
    METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE 有权
    制造半导体器件的方法

    公开(公告)号：US20090004842A1

    公开(公告)日：2009-01-01

    申请号：US11962442

    申请日：2007-12-21

    Applicant: Sung Hoon Lee

    Inventor： Sung Hoon Lee

    IPC: H01L21/4763

    CPC classification number: H01L21/76808 ,  H01L21/76831 ,  H01L21/76877 ,  H01L27/11517

    Abstract: The present invention relates to a method of fabricating a semiconductor device. According to the method, a first insulating layer having a contact hole formed therein is formed over a semiconductor substrate. A second insulating layer is gap filled within the contact hole. A third insulating layer having a trench formed therein is formed over the semiconductor substrate including the contact hole. The second insulating layer gap filled within the contact hole is removed. A contact plug and a bit line are formed within the contact hole and the trench.

    Abstract translation: 本发明涉及半导体器件的制造方法。 根据该方法，在半导体衬底上形成有形成有接触孔的第一绝缘层。 第二绝缘层在接触孔内填充间隙。 形成有沟槽的第三绝缘层形成在包括接触孔的半导体衬底的上方。 去除填充在接触孔内的第二绝缘层间隙。 接触插塞和位线形成在接触孔和沟槽内。

Patent Agency Ranking