公开(公告)号：US20130064013A1

公开(公告)日：2013-03-14

申请号：US13528886

申请日：2012-06-21

Applicant: JI-SANG LEE ,  KI HWAN CHOI

Inventor： JI-SANG LEE ,  KI HWAN CHOI

IPC: G11C16/04

CPC classification number: G11C11/5628 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/14 ,  G11C16/16 ,  G11C16/3418

Abstract: A non-volatile memory device, a data read method thereof and a recording medium are provided. The method includes receiving a data read command for a first word line in a memory cell array, reading data from a second word line adjacent to the first word line, and reading data from the first word line using a different voltage according to a state of the data read from the second word line. The number of read voltages used to distinguish an erased state and a first programmed state is greater than the number of read voltages used to distinguish a second programmed state and a third programmed state.

Abstract translation: 提供非易失性存储器件，其数据读取方法和记录介质。 该方法包括接收存储单元阵列中的第一字线的数据读取命令，从与第一字线相邻的第二字线读取数据，以及根据第一字线的状态从第一字线读取数据，使用不同的电压 从第二个字线读取数据。 用于区分擦除状态和第一编程状态的读取电压的数量大于用于区分第二编程状态和第三编程状态的读取电压的数量。

公开(公告)号：US08289774B2

公开(公告)日：2012-10-16

申请号：US12414973

申请日：2009-03-31

Applicant: Seung-Hyun Moon ,  Ki-Hwan Choi ,  Hyung-Gon Kim

Inventor： Seung-Hyun Moon ,  Ki-Hwan Choi ,  Hyung-Gon Kim

IPC: G11C11/34

CPC classification number: G11C16/0483 ,  G11C16/10

Abstract: Disclosed is an operating method of a flash memory device, which includes normal memory cells and dummy memory cells. The operating method includes programming the normal memory cells and programming the dummy memory cells. A dummy pass voltage used for programming the dummy memory cells is different from a normal pass voltage used for programming the normal memory cells.

Abstract translation: 公开了一种闪速存储器件的操作方法，其包括正常存储单元和虚拟存储单元。 操作方法包括对正常存储单元进行编程并编程虚拟存储单元。 用于对虚拟存储单元进行编程的虚拟通过电压与用于编程正常存储单元的正常通过电压不同。

公开(公告)号：US20090262576A1

公开(公告)日：2009-10-22

申请号：US12414973

申请日：2009-03-31

Applicant: Seung-Hyun MOON ,  Ki-Hwan CHOI ,  Hyung-Gon KIM

Inventor： Seung-Hyun MOON ,  Ki-Hwan CHOI ,  Hyung-Gon KIM

IPC: G11C16/06

CPC classification number: G11C16/0483 ,  G11C16/10

Abstract: Disclosed is an operating method of a flash memory device, which includes normal memory cells and dummy memory cells. The operating method includes programming the normal memory cells and programming the dummy memory cells. A dummy pass voltage used for programming the dummy memory cells is different from a normal pass voltage used for programming the normal memory cells.

Abstract translation: 公开了一种闪速存储器件的操作方法，其包括正常存储单元和虚拟存储单元。 操作方法包括对正常存储单元进行编程并编程虚拟存储单元。 用于对虚拟存储单元进行编程的虚拟通过电压与用于编程正常存储单元的正常通过电压不同。

公开(公告)号：US20080191785A1

公开(公告)日：2008-08-14

申请号：US11962436

申请日：2007-12-21

Applicant: Oh Suk KWON ,  Ki Hwan CHOI

Inventor： Oh Suk KWON ,  Ki Hwan CHOI

IPC: G05F3/02

CPC classification number: G11C5/145 ,  G11C16/30

Abstract: A high voltage generation circuit for use with a semiconductor memory device includes a plurality of high voltage generation units and a control circuit. The high voltage generation units generate high voltages having different voltage levels in response to corresponding clock signals. The control circuit generates clock signals, which do not toggle simultaneously, based on the voltage levels of the high voltages.

Abstract translation: 与半导体存储器件一起使用的高电压产生电路包括多个高压发生单元和控制电路。 高电压发生单元响应于对应的时钟信号产生具有不同电压电平的高电压。 控制电路基于高电压的电压电平产生不同时触发的时钟信号。

公开(公告)号：US20080158998A1

公开(公告)日：2008-07-03

申请号：US12049209

申请日：2008-03-14

Applicant: Ki-Hwan CHOI

Inventor： Ki-Hwan CHOI

IPC: G11C16/14 ,  G11C16/06

CPC classification number: G11C16/3468

Abstract: We describe a NAND flash memory device including a memory cell array formed on a substrate including a plurality of cell strings each including a string selecting transistor, a ground selecting transistor, and plural memory cells serially coupled between the string selecting transistor and the ground selecting transistor. A high voltage generator is configured to supply a bulk voltage to the substrate and an erase control circuit is configured to stepwise increase the bulk voltage during a first period of an erase operation and to maintain the bulk voltage substantially constant during a second period of the erase operation.

Abstract translation: 我们描述了一种NAND闪速存储器件，它包括一个形成在一个衬底上的存储单元阵列，该存储单元阵列包括多个单元串，每个单元串包括串选择晶体管，接地选择晶体管和串联在串选择晶体管和接地选择晶体管之间的多个存储单元 。 高电压发生器被配置为向衬底提供体电压，并且擦除控制电路被配置为在擦除操作的第一周期期间逐步增加体电压，并且在擦除的第二周期期间保持体电压基本恒定 操作。

公开(公告)号：US07366020B2

公开(公告)日：2008-04-29

申请号：US11670383

申请日：2007-02-01

Applicant: Ki-Hwan Choi

Inventor： Ki-Hwan Choi

IPC: G11C11/34

CPC classification number: G11C16/16 ,  G11C16/344

Abstract: We describe a NAND flash memory device including a memory cell array formed on a substrate including a plurality of cell strings each including a string selecting transistor, a ground selecting transistor, and plural memory cells serially coupled between the string selecting transistor and the ground selecting transistor. A high voltage generator is configured to supply a bulk voltage to the substrate and an erase control circuit is configured to stepwise increase the bulk voltage during a first period of an erase operation and to maintain the bulk voltage substantially constant during a second period of the erase operation.

Abstract translation: 我们描述了一种NAND闪速存储器件，它包括一个形成在一个衬底上的存储单元阵列，该存储单元阵列包括多个单元串，每个单元串包括串选择晶体管，接地选择晶体管和串联在串选择晶体管和接地选择晶体管之间的多个存储单元 。 高电压发生器被配置为向衬底提供体电压，并且擦除控制电路被配置为在擦除操作的第一周期期间逐步增加体电压，并且在擦除的第二周期期间保持体电压基本恒定 操作。

公开(公告)号：US20070183219A1

公开(公告)日：2007-08-09

申请号：US11670383

申请日：2007-02-01

Applicant: Ki-Hwan CHOI

Inventor： Ki-Hwan CHOI

IPC: G11C16/04 ,  G11C11/34

CPC classification number: G11C16/16 ,  G11C16/344

Abstract: We describe a NAND flash memory device including a memory cell array formed on a substrate including a plurality of cell strings each including a string selecting transistor, a ground selecting transistor, and plural memory cells serially coupled between the string selecting transistor and the ground selecting transistor. A high voltage generator is configured to supply a bulk voltage to the substrate and an erase control circuit is configured to stepwise increase the bulk voltage during a first period of an erase operation and to maintain the bulk voltage substantially constant during a second period of the erase operation.

Abstract translation: 我们描述了一种NAND闪速存储器件，它包括一个形成在一个衬底上的存储单元阵列，该存储单元阵列包括多个单元串，每个单元串包括串选择晶体管，接地选择晶体管和串联在串选择晶体管和接地选择晶体管之间的多个存储单元 。 高电压发生器被配置为向衬底提供体电压，并且擦除控制电路被配置为在擦除操作的第一周期期间逐步增加体电压，并且在擦除的第二周期期间保持体电压基本恒定 操作。

公开(公告)号：US07190624B2

公开(公告)日：2007-03-13

申请号：US11141732

申请日：2005-05-31

Applicant: Ki-Hwan Choi

Inventor： Ki-Hwan Choi

IPC: C11C11/34

CPC classification number: G11C16/3418 ,  G11C16/3468 ,  G11C16/3477

Abstract: The flash memory device according to the present invention includes an erase control circuit, used as a state machine, having embodied erase algorithm which can prevent flash memory cells from being over-erased. The erase control circuit, first, checks whether or not threshold voltages of selected cells reach a predetermined pre-verify voltage higher than the maximum value of a target threshold voltage range corresponding to the erased state. When at least one of the selected cells has its threshold voltage higher than the pre-verify voltage, a high voltage generator generates a bulk voltage that is increased step by step by a predetermined voltage level. And, when the selected cells all have threshold voltages equal to or less than the pre-verify voltage, the high voltage generator generates a constant bulk voltage. According to this bulk voltage control scheme, the number of flash memory cells over-erased at the erase operation is reduced reducing the total erase time.

Abstract translation: 根据本发明的闪速存储器件包括用作状态机的具有实现的擦除算法的擦除控制电路，其可以防止闪速存储器单元被过度擦除。 擦除控制电路首先检查所选择的单元的阈值电压是否达到比对应于擦除状态的目标阈值电压范围的最大值高的预定预验证电压。 当所选择的单元中的至少一个具有高于预验证电压的阈值电压时，高电压发生器产生逐步增加预定电压电平的体电压。 并且，当所选择的单元都具有等于或小于预验证电压的阈值电压时，高电压发生器产生恒定的体电压。 根据该体电压控制方案，在擦除操作时被擦除的闪存单元的数量减少，减少了总擦除时间。

公开(公告)号：US20050232022A1

公开(公告)日：2005-10-20

申请号：US11141732

申请日：2005-05-31

Applicant: Ki-Hwan Choi

Inventor： Ki-Hwan Choi

IPC: G11C11/34 ,  G11C16/34

CPC classification number: G11C16/3418 ,  G11C16/3468 ,  G11C16/3477

Abstract: The flash memory device according to the present invention includes an erase control circuit, used as a state machine, having embodied erase algorithm which can prevent flash memory cells from being over-erased. The erase control circuit, first, checks whether or not threshold voltages of selected cells reach a predetermined pre-verify voltage higher than the maximum value of a target threshold voltage range corresponding to the erased state. When at least one of the selected cells has its threshold voltage higher than the pre-verify voltage, a high voltage generator generates a bulk voltage that is increased step by step by a predetermined voltage level. And, when the selected cells all have threshold voltages equal to or less than the pre-verify voltage, the high voltage generator generates a constant bulk voltage. According to this bulk voltage control scheme, the number of flash memory cells over-erased at the erase operation is reduced reducing the total erase time.

公开(公告)号：US06407944B1

公开(公告)日：2002-06-18

申请号：US09533306

申请日：2000-03-23

Applicant: Ki-Hwan Choi ,  Jong-Min Park

Inventor： Ki-Hwan Choi ,  Jong-Min Park

IPC: G11C1606

CPC classification number: G11C16/107 ,  G11C16/3404

Abstract: A method is disclosed for preventing over-erasure in a nonvolatile memory device having a plurality of sectors, each sector including a main field and a redundant field. The method includes the steps of programming memory cells included in the main and redundant fields, erasing the memory cells included in the main and redundant fields, and programming over-erased cells of the memory cells included in the main and redundant fields. The main and redundant fields are included in a sector.

Abstract translation: 公开了一种用于防止具有多个扇区的非易失性存储器件中的过度擦除的方法，每个扇区包括主场和冗余场。 该方法包括以下步骤：对包括在主场和冗余场中的存储单元进行编程，擦除包括在主场和冗余场中的存储单元，以及编程包括在主场和冗余场中的存储单元的过擦除单元。 主要和冗余领域包括在一个部门。