公开(公告)号：US06590266B1

公开(公告)日：2003-07-08

申请号：US10064906

申请日：2002-08-28

申请人： Mu-Yi Liu ,  Tso-Hung Fan ,  Kwang-Yang Chan ,  Yen-Hung Yeh ,  Tao-Cheng Lu

发明人： Mu-Yi Liu ,  Tso-Hung Fan ,  Kwang-Yang Chan ,  Yen-Hung Yeh ,  Tao-Cheng Lu

IPC分类号： H01L2994

CPC分类号： H01L27/11266 ,  H01L27/112

摘要： A 2-bit mask ROM device and a fabrication method thereof are described. The 2-bit mask ROM device includes a substrate; a gate structure, disposed on a part of the substrate; a 2-bit code region, configured in the substrate beside both sides of the gate structure; at least one spacer, disposed on both sides of the gate structure; a buried drain region, configured in the substrate beside both sides of the spacer; a doped region, configured in the substrate between the buried drain region and the 2-bit code region, wherein the dopant type of the doped region is different from that for the 2-bit code region and the dopant concentration in the doped region is higher than that in the 2-bit code region; an insulation layer, disposed above the buried drain region; and a word line disposed on the gate structures along a same row.

摘要翻译： 描述2位掩模ROM器件及其制造方法。 2位掩模ROM器件包括衬底; 栅极结构，设置在所述衬底的一部分上; 2位代码区，配置在栅极结构的两侧旁边的基板中; 设置在所述栅极结构的两侧的至少一个间隔物; 掩埋漏极区域，被构造在所述衬底旁边的所述间隔物的两侧; 掺杂区域，配置在掩埋漏极区域和2位码区域之间的衬底中，其中掺杂区域的掺杂剂类型与2位码区域的掺杂区域不同，并且掺杂区域中的掺杂剂浓度更高 比在2位代码区域; 绝缘层，设置在所述掩埋漏极区域的上方; 以及沿同一行设置在栅极结构上的字线。

公开(公告)号：US06512696B1

公开(公告)日：2003-01-28

申请号：US09986932

申请日：2001-11-13

申请人： Tso-Hung Fan ,  Tao-Cheng Lu ,  Samuel Pan ,  Ta-Hui Wang

发明人： Tso-Hung Fan ,  Tao-Cheng Lu ,  Samuel Pan ,  Ta-Hui Wang

IPC分类号： G11C1604

CPC分类号： G11C16/12 ,  G11C16/14

摘要： A method of programming and erasing a SNNNS type non-volatile memory cell is provided. The programming operation is performed by channel hot electron injection from a drain side to an intermediate silicon nitride layer. The erasing operation is performed by channel hot hole injection from a drain side to an intermediate silicon nitride layer. The SNNNS type non-volatile memory cell provides highly efficient hot carrier injection under low applied voltages, both for programming and erasing operations. Thus, the present method provides improved performance characteristics such as shorter programming/erasing times and lower applied voltages.

摘要翻译： 提供了一种编程和擦除SNNNS型非易失性存储单元的方法。 通过从漏极侧到中间氮化硅层的通道热电子注入来进行编程动作。 擦除操作通过从漏极侧到中间氮化硅层的通道热空穴注入来进行。 SNNNS型非易失性存储单元在低施加电压下提供高效率的热载流子注入，用于编程和擦除操作。 因此，本方法提供改进的性能特征，例如较短的编程/擦除时间和较低的施加电压。

公开(公告)号：US06482706B1

公开(公告)日：2002-11-19

申请号：US10013982

申请日：2001-12-10

申请人： Yen-hung Yeh ,  Tso-Hung Fan ,  Mu Yi Liu ,  Kwang Yang Chan ,  Tao-Cheng Lu

发明人： Yen-hung Yeh ,  Tso-Hung Fan ,  Mu Yi Liu ,  Kwang Yang Chan ,  Tao-Cheng Lu

IPC分类号： H01L21336

CPC分类号： H01L27/11568 ,  H01L27/115

摘要： A method of scaling down device dimension using spacer to confine the buried drain implant, applicable for forming memory device such as substrate/oxide/nitride/oxide/silicon (SONOS) stacked device or nitride read only memory (NROM) device. A patterned conductive layer is used as a mask for forming a pocket doped region. A spacer is formed on a side-wall of the conductive layer. As the implantation region is confined by the side-wall, a buried drain region formed by drain implantation is reduced. Therefore, the effective channel length is not reduced due to the diffusion of the buried drain region. It is thus advantageous to scale down device dimension.

摘要翻译： 一种使用间隔物来缩小器件尺寸以限制掩埋漏极注入的方法，适用于形成诸如衬底/氧化物/氮化物/氧化物/硅（SONOS）堆叠器件或氮化物只读存储器（NROM）器件的存储器件。 使用图案化导电层作为形成口袋掺杂区域的掩模。 在导电层的侧壁上形成间隔物。 当注入区被侧壁限制时，通过漏极注入形成的掩埋漏极区减小。 因此，由于埋漏区的扩散，有效沟道长度不会降低。 因此有利的是缩小器件尺寸。

公开(公告)号：US06458642B1

公开(公告)日：2002-10-01

申请号：US09990159

申请日：2001-11-20

申请人： Yen-hung Yeh ,  Tso-Hung Fan ,  Mu Yi Liu ,  Kwang Yang Chan ,  Tao-Cheng Lu

发明人： Yen-hung Yeh ,  Tso-Hung Fan ,  Mu Yi Liu ,  Kwang Yang Chan ,  Tao-Cheng Lu

IPC分类号： H01L218238

CPC分类号： H01L27/11568 ,  H01L27/115 ,  Y10S438/954

摘要： A method of fabricating a SONOS device, in which a first silicon oxide layer, a trapping layer, and a second silicon oxide layer are formed on the substrate. Then, a mask pattern is formed over the substrate to serve as a mask in the implantation process for forming the buried bit-lines. Afterward, a portion of the mask pattern is removed to increase the gap size of the mask pattern, then a pocket ion implantation is performed to form a pocket doped region at the periphery of the buried bit-line by using the mask pattern as a mask. Subsequently, the mask pattern is removed and a thermal process is conducted using the trapping layer as a mask to form a buried bit-line oxide layer. A word-line is subsequently formed over the substrate.

摘要翻译： 一种制造SONOS器件的方法，其中在衬底上形成第一氧化硅层，俘获层和第二氧化硅层。 然后，在用于形成掩埋位线的注入工艺中，在衬底上形成掩模图案以用作掩模。 之后，去除掩模图案的一部分以增加掩模图案的间隙尺寸，然后通过使用掩模图案作为掩模，进行袋离子注入以在掩埋位线的周围形成凹坑掺杂区域 。 随后，去除掩模图案，并使用捕获层作为掩模进行热处理，以形成掩埋的位线氧化物层。 随后在衬底上形成字线。

公开(公告)号：US5648128A

公开(公告)日：1997-07-15

申请号：US659341

申请日：1996-06-06

申请人： Ching-Fa Yeh ,  Tso-Hung Fan

发明人： Ching-Fa Yeh ,  Tso-Hung Fan

IPC分类号： H01L21/316 ,  B06B1/20

CPC分类号： H01L21/316

摘要： A liquid phase deposition method involves a reaction mixture composed of a hydrosilicofluoric acid aqueous solution supersaturated with silicon dioxide, and a semiconductor substrate disposed therein. The reaction mixture is treated with an ultrasonic oscillation at a frequency ranging between 20 and 100 KHz and at a temperature ranging between 10.degree. and 50.degree. C. for accelerating the growth rate of a silicon dioxide layer formed on the semiconductor substrate.

摘要翻译： 液相沉积方法包括由二氧化硅过饱和的氢硅氟酸水溶液和设置在其中的半导体衬底组成的反应混合物。 将反应混合物用频率范围在20和100KHz之间的超声波振荡处理，并且在10℃和50℃之间的温度下进行处理，以加速在半导体衬底上形成的二氧化硅层的生长速率。