公开(公告)号：US07012305B2

公开(公告)日：2006-03-14

申请号：US10708171

申请日：2004-02-12

申请人： Shin Su ,  Chun-Hsiang Lai ,  Chia-Ling Lu ,  Yen-Hung Yeh ,  Tao-Cheng Lu

发明人： Shin Su ,  Chun-Hsiang Lai ,  Chia-Ling Lu ,  Yen-Hung Yeh ,  Tao-Cheng Lu

IPC分类号： H01L23/62

CPC分类号： H01L27/0262 ,  H01L29/7436

摘要： An electro-static discharge (ESD) protection circuit for a dual polarity I/O pad is provided. The protection circuit includes a substrate of first type; a deep well region of second type disposed in the first type substrate; a well region of first type disposed in the second type deep well region; a first transistor disposed over the well region of first type, wherein the first transistor has a first source, a first gate and a first drain; a second transistor disposed over the substrate of first type, wherein the second transistor has a second source, a second gate and a second drain, and the second source is connected with the first drain, and both of them are disposed in a portion of the well region of first type, the deep well region of second type and the substrate of first type; a first doped region is disposed in the first type well region and laterally adjacent to the first source; a second doped region is disposed in the substrate of first type and laterally adjacent to the second drain.

摘要翻译： 提供用于双极性I / O焊盘的静电放电（ESD）保护电路。 保护电路包括第一类型的衬底; 设置在所述第一类型基板中的第二类型的深阱区域; 设置在第二类型深井区域中的第一类型井区域; 第一晶体管设置在第一类型的阱区上，其中第一晶体管具有第一源极，第一栅极和第一漏极; 设置在第一类型的衬底上的第二晶体管，其中第二晶体管具有第二源极，第二栅极和第二漏极，并且第二源极与第一漏极连接，并且它们都被布置在 第一类井区，第二类深井区和第一类的基底; 第一掺杂区域设置在第一类型阱区域中并且横向邻近于第一源极; 第二掺杂区域设置在第一类型的衬底中并且横向邻近于第二漏极。

公开(公告)号：US07002849B2

公开(公告)日：2006-02-21

申请号：US10983019

申请日：2004-11-05

申请人： Tso-Hung Fan ,  Yen-Hung Yeh ,  Kwang-Yang Chan ,  Mu-Yi Liu ,  Tao-Cheng Lu

发明人： Tso-Hung Fan ,  Yen-Hung Yeh ,  Kwang-Yang Chan ,  Mu-Yi Liu ,  Tao-Cheng Lu

IPC分类号： G11C16/04 ,  G11C5/06 ,  G06F12/00

CPC分类号： G11C16/0466 ,  G11C16/10 ,  G11C16/14

摘要： A method for programming and erasing a non-volatile memory with a nitride tunneling layer is described. The non-volatile memory is programmed by applying a first voltage to the gate and grounding the substrate to turn on a channel between the source and the drain, and applying a second voltage to the drain and grounding the source to induce a current in the channel and thereby to generate hot electrons therein. The hot electrons are injected into a charge-trapping layer of the non-volatile and trapped therein through the nitride tunneling layer. The non-volatile memory is erased by applying a first positive bias to the drain, applying a second positive bias to the gate, and grounding the source and the substrate to generate hot electron holes in the channel region. The hot electron holes are injected into the charge-trapping layer through the nitride tunneling layer.

公开(公告)号：US20050269641A1

公开(公告)日：2005-12-08

申请号：US10904475

申请日：2004-11-12

申请人： Chun-Hsiang Lai ,  Shin Su ,  Chia-Ling Lu ,  Yen-Hung Yeh ,  Tao-Cheng Lu

发明人： Chun-Hsiang Lai ,  Shin Su ,  Chia-Ling Lu ,  Yen-Hung Yeh ,  Tao-Cheng Lu

IPC分类号： H01L23/60 ,  H01L27/02 ,  H01L29/72 ,  H01L29/74

CPC分类号： H01L27/0266 ,  H01L29/7436 ,  H01L29/87

摘要： An electrostatic discharge (ESD) protection circuit coupled to an input pad comprises a diode formed in a substrate and coupled to the input pad; a P deep well formed in the substrate; an N well formed in the P deep well; a first P+ doped region in the N well; and an NMOS transistor formed on the substrate, comprising a gate, a source and a drain, wherein the drain is formed in the N well and coupled to a Vcc, and the source is formed in the P deep well; and a second P+ doped region formed in the P deep well. The ESD protection circuit uses a smaller area than the conventional ESD protection circuit.

摘要翻译： 耦合到输入焊盘的静电放电（ESD）保护电路包括形成在衬底中并耦合到输入焊盘的二极管; 在衬底中形成的P阱; 在P深井中形成N井; N阱中的第一P +掺杂区; 以及形成在所述衬底上的NMOS晶体管，包括栅极，源极和漏极，其中所述漏极形成在所述N阱中并且耦合到Vcc，并且所述源极形成在所述P阱中; 以及形成在P深井中的第二P +掺杂区域。 ESD保护电路使用比常规ESD保护电路更小的面积。

公开(公告)号：US20050133868A1

公开(公告)日：2005-06-23

申请号：US10708171

申请日：2004-02-12

申请人： Shin Su ,  Chun-Hsiang Lai ,  Chia-Ling Lu ,  Yen-Hung Yeh ,  Tao-Cheng Lu

发明人： Shin Su ,  Chun-Hsiang Lai ,  Chia-Ling Lu ,  Yen-Hung Yeh ,  Tao-Cheng Lu

IPC分类号： H01L23/60 ,  H01L23/62 ,  H01L27/02 ,  H01L29/74

CPC分类号： H01L27/0262 ,  H01L29/7436

摘要： An electro-static discharge (ESD) protection circuit for a dual polarity I/O pad is provided. The protection circuit includes a substrate of first type; a deep well region of second type disposed in the first type substrate; a well region of first type disposed in the second type deep well region; a first transistor disposed over the well region of first type, wherein the first transistor has a first source, a first gate and a first drain; a second transistor disposed over the substrate of first type, wherein the second transistor has a second source, a second gate and a second drain, and the second source is connected with the first drain, and both of them are disposed in a portion of the well region of first type, the deep well region of second type and the substrate of first type; a first doped region is disposed in the first type well region and laterally adjacent to the first source; a second doped region is disposed in the substrate of first type and laterally adjacent to the second drain.

摘要翻译： 提供用于双极性I / O焊盘的静电放电（ESD）保护电路。 保护电路包括第一类型的衬底; 设置在所述第一类型基板中的第二类型的深阱区域; 设置在第二类型深井区域中的第一类型井区域; 第一晶体管设置在第一类型的阱区上，其中第一晶体管具有第一源极，第一栅极和第一漏极; 设置在第一类型的衬底上的第二晶体管，其中第二晶体管具有第二源极，第二栅极和第二漏极，并且第二源极与第一漏极连接，并且它们都被布置在 第一类井区，第二类深井区和第一类的基底; 第一掺杂区域设置在第一类型阱区域中并且横向邻近于第一源极; 第二掺杂区域设置在第一类型的衬底中并且横向邻近于第二漏极。

公开(公告)号：US20050082597A1

公开(公告)日：2005-04-21

申请号：US10983019

申请日：2004-11-05

申请人： Tso-Hung Fan ,  Yen-Hung Yeh ,  Kwang-Yang Chan ,  Mu-Yi Liu ,  Tao-Cheng Lu

发明人： Tso-Hung Fan ,  Yen-Hung Yeh ,  Kwang-Yang Chan ,  Mu-Yi Liu ,  Tao-Cheng Lu

IPC分类号： G11C16/04 ,  G11C16/10 ,  G11C16/14 ,  H01L29/788

CPC分类号： G11C16/0466 ,  G11C16/10 ,  G11C16/14

摘要： A method for programming and erasing a non-volatile memory with a nitride tunneling layer is described. The non-volatile memory is programmed by applying a first voltage to the gate and grounding the substrate to turn on a channel between the source and the drain, and applying a second voltage to the drain and grounding the source to induce a current in the channel and thereby to generate hot electrons therein. The hot electrons are injected into a charge-trapping layer of the non-volatile and trapped therein through the nitride tunneling layer. The non-volatile memory is erased by applying a first positive bias to the drain, applying a second positive bias to the gate, and grounding the source and the substrate to generate hot electron holes in the channel region. The hot electron holes are injected into the charge-trapping layer through the nitride tunneling layer.

摘要翻译： 描述了用氮化物隧穿层编程和擦除非易失性存储器的方法。 非易失性存储器通过向栅极施加第一电压并使衬底接地以接通源极和漏极之间的沟道并且向漏极施加第二电压并且将源接地以感应通道中的电流来编程 从而在其中产生热电子。 热电子通过氮化物隧穿层注入到非挥发性的电荷捕获层中并被捕获在其中。 通过向漏极施加第一正偏压，向栅极施加第二正偏压，并且将源极和衬底接地以在沟道区域中产生热电子空穴来擦除非易失性存储器。 热电子空穴通过氮化物隧穿层注入电荷捕获层。

公开(公告)号：US20050047036A1

公开(公告)日：2005-03-03

申请号：US10854792

申请日：2004-05-27

申请人： Meng-Huang Liu ,  Chun-Hsiang Lai ,  Shin Su ,  Yen-Hung Yeh ,  Chia-Ling Lu ,  Tao-Cheng Lu

发明人： Meng-Huang Liu ,  Chun-Hsiang Lai ,  Shin Su ,  Yen-Hung Yeh ,  Chia-Ling Lu ,  Tao-Cheng Lu

IPC分类号： H01L23/60 ,  H01L27/02 ,  H02H9/00

CPC分类号： H01L27/0266

摘要： In an ESD protection structure and method utilizing substrate triggering for a high-voltage tolerant pad on a substrate, an ESD protection device has a source connected to the pad and a gate and a drain both connected to a ground, and a substrate-triggering control circuit is used to keep the substrate at a low voltage during a normal operation, and pumping the substrate to a high voltage during an ESD event for the ESD protection device to be triggered much easier. The substrate-triggering control circuit is implemented with an active device, thereby reducing the chip size for the circuit and the loading effect on the pad.

摘要翻译： 在ESD保护结构和方法中，利用衬底触发用于衬底上的高耐压焊盘，ESD保护器件具有连接到焊盘的源极和连接到地的栅极和漏极，以及衬底触发控制 电路用于在正常操作期间将衬底保持在低电压，并且在ESD事件期间将衬底泵送到高电压以使ESD保护器件被触发得更容易。 基板触发控制电路由有源器件实现，从而减小电路的芯片尺寸和对焊盘的负载效应。

公开(公告)号：US06709921B2

公开(公告)日：2004-03-23

申请号：US09967717

申请日：2001-09-27

申请人： Yen-hung Yeh ,  Tso-Hung Fan ,  Wen-Jer Tsai ,  Mu-Yi Liu ,  Kwang Yang Chan ,  Tao-Cheng Lu

发明人： Yen-hung Yeh ,  Tso-Hung Fan ,  Wen-Jer Tsai ,  Mu-Yi Liu ,  Kwang Yang Chan ,  Tao-Cheng Lu

IPC分类号： H01L21336

CPC分类号： H01L29/66825 ,  H01L21/28273 ,  H01L29/7887

摘要： A fabrication method for a flash memory device with a split floating gate is described. The method provides a substrate, wherein an oxide layer and a patterned sacrificial layer are sequentially formed on the substrate. Ion implantation is then conducted to form source/drain regions with lightly doped source/drain regions in the substrate beside the sides of the patterned sacrificial layer using the patterned sacrificial layer as a mask. Isotropic etching is further conducted to remove a part of the patterned sacrificial layer, followed by forming two conductive spacers on the sidewalls of the patterned sacrificial layer. The patterned sacrificial layer and oxide layer that is exposed by the two conductive spacers are then removed to form two floating gates. Subsequently, a dielectric layer and a control gate are formed on the substrate.

摘要翻译： 描述了具有分离浮动栅极的闪速存储器件的制造方法。 该方法提供了一种衬底，其中氧化物层和图案化的牺牲层依次形成在衬底上。 然后使用图案化的牺牲层作为掩模，进行离子注入，以在图案化牺牲层的侧面旁边的衬底中形成具有轻掺杂的源/漏区的源/漏区。 进一步进行各向同性蚀刻以去除图案化牺牲层的一部分，然后在图案化牺牲层的侧壁上形成两个导电间隔物。 然后去除由两个导电间隔物暴露的图案化牺牲层和氧化物层以形成两个浮动栅极。 随后，在基板上形成电介质层和控制栅极。

公开(公告)号：US07573102B2

公开(公告)日：2009-08-11

申请号：US11496490

申请日：2006-08-01

申请人： Meng-Huang Liu ,  Chun-Hsiang Lai ,  Shin Su ,  Yen-Hung Yeh ,  Chia-Ling Lu ,  Tao-Cheng Lu

发明人： Meng-Huang Liu ,  Chun-Hsiang Lai ,  Shin Su ,  Yen-Hung Yeh ,  Chia-Ling Lu ,  Tao-Cheng Lu

IPC分类号： H01L29/72

CPC分类号： H01L27/0266

摘要： In an ESD protection structure and method utilizing substrate triggering for a high-voltage tolerant pad on a substrate, an ESD protection device has a source connected to the pad and a gate and a drain both connected to a ground, and a substrate-triggering control circuit is used to keep the substrate at a low voltage during a normal operation, and pumping the substrate to a high voltage during an ESD event for the ESD protection device to be triggered much easier. The substrate-triggering control circuit is implemented with an active device, thereby reducing the chip size for the circuit and the loading effect on the pad.

摘要翻译： 在ESD保护结构和方法中，利用衬底触发用于衬底上的高耐压焊盘，ESD保护器件具有连接到焊盘的源极和连接到地的栅极和漏极，以及衬底触发控制 电路用于在正常操作期间将衬底保持在低电压，并且在ESD事件期间将衬底泵送到高电压以使ESD保护器件被触发得更容易。 基板触发控制电路由有源器件实现，从而减小电路的芯片尺寸和对焊盘的负载效应。

公开(公告)号：US07087968B1

公开(公告)日：2006-08-08

申请号：US11141284

申请日：2005-05-31

申请人： Chun-Hsiang Lai ,  Yen-Hung Yeh ,  Chia-Ling Lu

发明人： Chun-Hsiang Lai ,  Yen-Hung Yeh ,  Chia-Ling Lu

IPC分类号： H01L23/62

CPC分类号： H01L27/0259 ,  H01L29/7436

摘要： An ESD protection circuit is adapted for an integrated circuit with a first power source and a second power source. The ESD protection circuit comprises a first silicon controlled rectifier (SCR), a second silicon controlled rectifier, and a parasitic diode. The gate of the first silicon controlled rectifier is coupled to a first power source, and the gate of the second silicon controlled rectifier is also coupled to the first power source line.

摘要翻译： ESD保护电路适用于具有第一电源和第二电源的集成电路。 ESD保护电路包括第一可控硅整流器（SCR），第二可控硅整流器和寄生二极管。 第一可控硅整流器的栅极耦合到第一电源，并且第二可控硅整流器的栅极也耦合到第一电源线。

公开(公告)号：US06790730B2

公开(公告)日：2004-09-14

申请号：US10156325

申请日：2002-05-24

申请人： Tso-Hung Fan ,  Yen-Hung Yeh ,  Kwang-Yang Chan ,  Mu-Yi Liu ,  Tao-Cheng Lu

发明人： Tso-Hung Fan ,  Yen-Hung Yeh ,  Kwang-Yang Chan ,  Mu-Yi Liu ,  Tao-Cheng Lu

IPC分类号： H01L21336

CPC分类号： H01L27/11253 ,  H01L21/26586 ,  H01L27/112

摘要： A fabrication method for a mask read only memory device is described. The method provides a substrate, and a doped conductive layer is formed on the substrate. After this, the doped conductive layer is patterned to form a plurality of bar-shaped doped conductive layers, followed by forming a dielectric layer on the substrate and on the bar-shaped conductive layers by thermal oxidation. A plurality of diffusion regions are concurrently formed under the bar-shaped conductive layers in the substrate. A patterned conductive layer is further formed on the dielectric layer.

摘要翻译： 描述了一种用于掩模只读存储器件的制造方法。 该方法提供衬底，并且在衬底上形成掺杂导电层。 之后，将掺杂的导电层图案化以形成多个棒状掺杂导电层，随后通过热氧化在基板上和棒状导电层上形成电介质层。 多个扩散区同时形成在基板中的棒状导电层的下方。 在电介质层上进一步形成图案化的导电层。