公开(公告)号：US06187645B1

公开(公告)日：2001-02-13

申请号：US09233354

申请日：1999-01-19

Applicant: Tony Lin ,  Coming Chen ,  Jih-Wen Chou

Inventor： Tony Lin ,  Coming Chen ,  Jih-Wen Chou

IPC: H01L21336

CPC classification number: H01L29/6659 ,  H01L21/28035

Abstract: A method for manufacturing semiconductor device. The method includes the steps of providing a substrate that has a gate structure thereon, and then forming offset spacers on the sidewalls of the gate structure. Thereafter, a thin oxide annealing operation is conducted, and then a first ion implantation is carried out using the gate structure and the offset spacers as a mask to form lightly doped drain regions in the substrate. Subsequently, secondary spacers are formed on the exterior sidewalls of the offset spacers. Finally, a second ion implantation is carried out using the gate structure, the offset spacers and the secondary spacers as a mask to form source/drain regions within the lightly doped drain regions.

Abstract translation: 一种半导体器件的制造方法。 该方法包括以下步骤：提供其上具有栅极结构的衬底，然后在栅极结构的侧壁上形成偏置间隔物。 此后，进行薄氧化物退火操作，然后使用栅极结构和偏移间隔物作为掩模进行第一离子注入，以在衬底中形成轻掺杂的漏极区。 随后，在偏置间隔物的外侧壁上形成二次间隔物。 最后，使用栅极结构，偏移间隔物和次级间隔物作为掩模进行第二离子注入，以在轻掺杂漏极区内形成源/漏区。

公开(公告)号：US06177336B1

公开(公告)日：2001-01-23

申请号：US09187245

申请日：1998-11-06

Applicant: Tony Lin ,  Wen-Kuan Yeh ,  Coming Chen ,  Jih-Wen Chou

Inventor： Tony Lin ,  Wen-Kuan Yeh ,  Coming Chen ,  Jih-Wen Chou

IPC: H01L214763

CPC classification number: H01L29/66545 ,  H01L29/66537

Abstract: A method for fabricating a metal-oxide semiconductor (MOS) transistor is provided. The method has steps of sequentially forming an oxide layer, a polysilicon layer and a cap layer on a semiconductor substrate to form a first-stage gate. An interchangeable source/drain region with a lightly doped drain (LDD) structure is formed in the substrate at each side of the first-stage gate. An insulating layer is formed over the substrate, and is planarized so as to exposed the cap layer. Removing the exposed cap layer forms an opening that exposes the polysilicon layer. Using the insulating layer as a mask, a self-aligned selective local implantation process is performed to form a threshold-voltage doped region and an anti-punch-through doped region below the oxide layer in the substrate. A conductive layer is formed over the substrate to fill the opening. A chemical mechanical polishing process is performed to expose the insulating layer so that a remaining portion of the conductive layer fills the opening to form together with the polysilicon layer and the oxide layer to serve as an gate structure.

Abstract translation: 提供一种制造金属氧化物半导体（MOS）晶体管的方法。 该方法具有在半导体衬底上依次形成氧化物层，多晶硅层和覆盖层以形成第一级栅极的步骤。 在第一级栅极的每一侧的衬底中形成具有轻掺杂漏极（LDD）结构的可互换的源极/漏极区域。 绝缘层形成在衬底上，并被平坦化以使盖层露出。 去除暴露的盖层形成暴露多晶硅层的开口。 使用绝缘层作为掩模，执行自对准选择性局部注入工艺以在衬底中的氧化物层下方形成阈值电压掺杂区域和抗穿通掺杂区域。 导电层形成在衬底上以填充开口。 执行化学机械抛光工艺以暴露绝缘层，使得导电层的剩余部分填充开口以与多晶硅层和氧化物层一起形成以用作栅极结构。

公开(公告)号：US06174778B1

公开(公告)日：2001-01-16

申请号：US09212055

申请日：1998-12-15

Applicant: Coming Chen ,  Tony Lin ,  Jih-Wen Chou

Inventor： Coming Chen ,  Tony Lin ,  Jih-Wen Chou

IPC: H01L21336

CPC classification number: H01L29/6659 ,  H01L21/26586 ,  H01L29/1045 ,  H01L29/1083

Abstract: A method of fabricating a metal oxide semiconductor includes formation of a gate on a substrate. A source/drain extension is formed beside the gate in the substrate. An ion implantation step is performed to implant heavy impurities with a low diffusion coefficient in the substrate. A heavily doped halo region is formed in the substrate below the source/drain extension. A tilt-angled halo implantation step is performed to form a halo-implanted region in the substrate to the side of the source/drain extension below the gate.

Abstract translation: 制造金属氧化物半导体的方法包括在基板上形成栅极。 在衬底的栅极旁边形成源极/漏极延伸部。 进行离子注入步骤以在衬底中植入具有低扩散系数的重杂质。 在源极/漏极延伸部下方的衬底中形成重掺杂的卤素区域。 进行倾斜角度的晕圈注入步骤以在衬底中的栅极下方的源极/漏极延伸侧形成卤素注入区域。

公开(公告)号：US6165913A

公开(公告)日：2000-12-26

申请号：US957922

申请日：1997-10-27

Applicant: Tony Lin ,  Heng-Sheng Huang

Inventor： Tony Lin ,  Heng-Sheng Huang

IPC: H01L21/336 ,  H01L29/49 ,  H01L21/3205 ,  H01L21/308

CPC classification number: H01L29/6659 ,  H01L29/4983 ,  H01L29/6656

Abstract: A method for manufacturing spacers comprising the steps of first providing a semiconductor substrate having a gate electrode already formed thereon, and then sequentially depositing oxide, silicon nitride and oxide over the gate electrode and the substrate to form a first oxide layer, a silicon nitride layer and a second oxide layer. Subsequently, the second oxide layer is etched to form an oxide spacer above the silicon nitride layer. Thereafter, using the oxide spacer as a mask, a dry etching method having a high etching selectivity ratio for silicon nitride/oxide is used to etch the silicon nitride layer to form a silicon nitride spacer. Finally, the oxide spacer is removed using an oxide dip method. The silicon nitride spacers of this invention can have a greater thickness, more thickness uniformity, and a higher reliability for hot carriers. In addition, the method used in the invention can have a better control over the thickness.

Abstract translation: 一种用于制造间隔物的方法，包括以下步骤：首先提供其上已经形成有栅电极的半导体衬底，然后在栅电极和衬底上依次沉积氧化物，氮化硅和氧化物以形成第一氧化物层，氮化硅层 和第二氧化物层。 随后，蚀刻第二氧化物层以在氮化硅层上形成氧化物间隔物。 此后，使用氧化物间隔物作为掩模，使用对于氮化硅/氧化物具有高蚀刻选择性比的干蚀刻方法来蚀刻氮化硅层以形成氮化硅间隔物。 最后，使用氧化物浸渍法除去氧化物间隔物。 本发明的氮化硅间隔物可以具有更大的厚度，更多的厚度均匀性和对热载体的更高的可靠性。 此外，本发明中使用的方法可以更好地控制厚度。

公开(公告)号：US6153478A

公开(公告)日：2000-11-28

申请号：US14755

申请日：1998-01-28

Applicant: Tony Lin ,  Wen-Kuan Yeh ,  Heng-Sheng Huang

Inventor： Tony Lin ,  Wen-Kuan Yeh ,  Heng-Sheng Huang

IPC: H01L21/762 ,  H01L21/00

CPC classification number: H01L21/76235

Abstract: The process includes the following steps. At first, a masking layer is formed over the semiconductor substrate. A portion of the masking layer is then removed to form an opening to the semiconductor substrate. Sidewall spacers are formed on the opening and a portion of the semiconductor substrate is removed to form a trench, through an aperture defined by the sidewall spacers. The sidewall spacers is then removed and a liner layer is formed conformably over the trench.

Abstract translation: 该过程包括以下步骤。 首先，在半导体衬底上形成掩模层。 然后去除掩模层的一部分以形成到半导体衬底的开口。 侧壁间隔件形成在开口上，并且半导体衬底的一部分被去除以形成通过由侧壁间隔件限定的孔的沟槽。 然后去除侧壁间隔物，并且衬垫层顺应地形成在沟槽上。

公开(公告)号：US6083783A

公开(公告)日：2000-07-04

申请号：US94053

申请日：1998-06-09

Applicant: Tony Lin ,  Wen-Kuan Yeh ,  Jenn Tsao

Inventor： Tony Lin ,  Wen-Kuan Yeh ,  Jenn Tsao

IPC: H01L21/8238

CPC classification number: H01L21/823807

Abstract: A method of manufacturing a complementary metal-oxide-semiconductor that utilizes a slight change in the patterned photoresist layer for forming the lightly doped drain structure of an NMOS and the halo implantation region during CMOS fabrication. By forming a photoresist layer that exposes the p-well region where a well pickup structure is to be formed, the distance between the photoresist layer and the gate is increased, thereby eliminating the restrictions imposed upon the tilt angle in a halo implantation. Later, the lightly doped n-type impurities in the well pickup region can be compensated for by the p-type impurity implantation when the PMOS source/drain regions are formed. Hence, the lightly doped n-type well pickup region can be reverted to a p-type impurity doped region.

Abstract translation: 制造互补金属氧化物半导体的方法，其利用图案化的光致抗蚀剂层中的轻微变化，以在CMOS制造期间形成NMOS的轻掺杂漏极结构和卤注入区。 通过形成露出要形成阱拾取结构的p阱区的光致抗蚀剂层，光致抗蚀剂层和栅极之间的距离增加，从而消除了在光晕注入中施加在倾斜角上的限制。 然后，当形成PMOS源极/漏极区域时，可以通过p型杂质注入来补偿阱拾取区域中的轻掺杂n型杂质。 因此，轻掺杂的n型阱拾取区域可以被还原成p型杂质掺杂区域。

公开(公告)号：US06064107A

公开(公告)日：2000-05-16

申请号：US56276

申请日：1998-04-07

Applicant: Wen-Kuan Yeh ,  Tony Lin ,  Heng-Sheng Huang

Inventor： Wen-Kuan Yeh ,  Tony Lin ,  Heng-Sheng Huang

IPC: H01L21/336 ,  H01L29/423 ,  H01L29/49 ,  H01L29/00

CPC classification number: H01L29/66583 ,  H01L29/4983 ,  H01L29/4991 ,  H01L29/42376 ,  H01L29/4238 ,  H01L29/665

Abstract: A semiconductor device comprises a semiconductor substrate, a source/drain region formed in the substrate, a gate oxide layer on the substrate between the source/drain region, a conductive layer on the gate oxide layer, a spacer around a side wall of the gate, and an air gap between the gate and the spacer. The spacer is not directly connected with the gate. The air gap is formed between the gate and the spacer.

Abstract translation: 半导体器件包括半导体衬底，形成在衬底中的源极/漏极区，源极/漏极区之间的衬底上的栅极氧化物层，栅极氧化物层上的导电层，栅极侧壁周围的间隔物 ，以及栅极和间隔物之间​​的气隙。 间隔件不直接与门连接。 气隙形成在栅极和间隔物之间​​。

公开(公告)号：US6063660A

公开(公告)日：2000-05-16

申请号：US52685

申请日：1998-03-31

Applicant: Hua-Chou Tseng ,  Tony Lin ,  Horng-Nan Chern

Inventor： Hua-Chou Tseng ,  Tony Lin ,  Horng-Nan Chern

IPC: H01L21/8242 ,  H01L27/108

CPC classification number: H01L27/10852 ,  H01L27/10817

Abstract: A fabricating method and a structure of a stacked-type capacitor is provided comprising forming a first dielectric layer having a first via on a semiconductor substrate. A first conductive layer is filled into the first via. Then, insulating layers and dielectric layers are formed. A photolithography step is used to form a second dendriform via in the insulating layers and the dielectric layers. A second conductive layer is filled in the second dendriform via. The insulating layers and conductive layers are removed to form a dendriform lower electrode. The dendriform electrode provides a larger surface area to increase capacitance. Further, a polysilicon layer of hemispherical grains is formed to increase the surface area of the lower electrode.

Abstract translation: 提供叠层型电容器的制造方法和结构，包括在半导体衬底上形成具有第一通孔的第一介电层。 第一导电层被填充到第一通孔中。 然后，形成绝缘层和电介质层。 使用光刻步骤在绝缘层和电介质层中形成第二树状通道。 第二导电层填充在第二树状通孔中。 去除绝缘层和导电层以形成树状下电极。 树状电极提供更大的表面积以增加电容。 此外，形成半球状晶粒的多晶硅层以增加下电极的表面积。

公开(公告)号：US6015753A

公开(公告)日：2000-01-18

申请号：US103888

申请日：1998-06-24

Applicant: Tony Lin ,  Hua-Chou Tseng ,  Water Lur

Inventor： Tony Lin ,  Hua-Chou Tseng ,  Water Lur

IPC: H01L21/28 ,  H01L21/285 ,  H01L21/336 ,  H01R13/10

CPC classification number: H01L29/665 ,  H01L21/28052 ,  H01L21/28518 ,  H01L29/41783

Abstract: A method of forming a self-aligned salicide is provided. The invention twice performs selective epitaxial growth to form an amorphous silicon layer on gate electrodes and source/drain regions of a substrate after forming the gate electrodes and the source/drain regions. Then, a molybdenum impurity is doped to perform a silicidation process and to convert a metal deposited on the substrate into a salicide layer.

Abstract translation: 提供了形成自对准硅化物的方法。 本发明在形成栅极电极和源极/漏极区域之后，两次执行选择性外延生长以在衬底的栅极电极和源极/漏极区域上形成非晶硅层。 然后，掺杂钼杂质以进行硅化工艺并将沉积在衬底上的金属转化成自对准硅化物层。

公开(公告)号：US6013569A

公开(公告)日：2000-01-11

申请号：US888752

申请日：1997-07-07

Applicant: Water Lur ,  Tony Lin

Inventor： Water Lur ,  Tony Lin

IPC: H01L21/28 ,  H01L21/336 ,  H01L21/335 ,  H01L21/76 ,  H01L21/762

CPC classification number: H01L29/6659 ,  H01L21/28247 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/66545

Abstract: Silicidation of a polysilicon line having frcc upper sidewalls is performed so that no stress is applied to the sidewalls of the polysilicon line, resulting in the formation of a reduced stress silicide structure. This is accomplished by forming a polysilicon line having spacers on either side which extend above the upper surface of the polysilicon line but which are spaced from the edge of the polysilicon line. A layer of a metal such as titanium or tungsten is provided in contact with the top surface polysilicon line. The structure is annealed to cause the metal to react with the polysilicon to form a layer of silicide. Since the upper side portions of the polysilicon line are spaced away from the spacers during the silicidation anneal, the growing silicide region has room to expand without being subjected to lateral stresses in the silicidation process. The suicide is formed in a reduced stress condition, as compared to conventional processes, so that the silicide layer produced will be more readily converted to the desired low resistivity phase of silicide.

Abstract translation: 执行具有frcc上侧壁的多晶硅线的硅化，使得没有应力施加到多晶硅线的侧壁，导致形成应力减小的硅化物结构。 这是通过在多晶硅线的上表面上方延伸但与多晶硅线的边缘间隔开的任一侧上形成具有间隔物的多晶硅线来实现的。 提供与顶表面多晶硅线接触的诸如钛或钨的金属层。 将该结构退火以使金属与多晶硅反应形成一层硅化物。 由于在硅化退火期间多晶硅线的上侧部分与间隔物间隔开，所以生长的硅化物区域具有膨胀的空间，而不会在硅化过程中受到横向应力。 与常规方法相比，自杀在降低的应力条件下形成，使得所生成的硅化物层将更容易地转化为期望的硅化物的低电阻率相。