公开(公告)号：US06211086B1

公开(公告)日：2001-04-03

申请号：US09328244

申请日：1999-06-08

Applicant: Tzung-Han Lee ,  Horng-Nan Chern

Inventor： Tzung-Han Lee ,  Horng-Nan Chern

IPC: H01L2144

CPC classification number: H01L21/7684 ,  H01L21/31053 ,  H01L21/3212 ,  H01L21/76819

Abstract: A method for forming a semiconductor device with avoiding chemical mechanical polishing caused residue on uncompleted fields of wafer edge is disclosed. The method comprising removing all conductive layers and silicon nitride layers on the uncompleted fields, thereby the height of the uncompleted fields will not higher than the height of the semiconductor device.

Abstract translation: 公开了一种用于形成半导体器件的避免化学机械抛光的方法，导致晶片边缘未完成场的残留。 该方法包括去除未完成场上的所有导电层和氮化硅层，从而未完成场的高度不会高于半导体器件的高度。

公开(公告)号：US6063660A

公开(公告)日：2000-05-16

申请号：US52685

申请日：1998-03-31

Applicant: Hua-Chou Tseng ,  Tony Lin ,  Horng-Nan Chern

Inventor： Hua-Chou Tseng ,  Tony Lin ,  Horng-Nan Chern

IPC: H01L21/8242 ,  H01L27/108

CPC classification number: H01L27/10852 ,  H01L27/10817

Abstract: A fabricating method and a structure of a stacked-type capacitor is provided comprising forming a first dielectric layer having a first via on a semiconductor substrate. A first conductive layer is filled into the first via. Then, insulating layers and dielectric layers are formed. A photolithography step is used to form a second dendriform via in the insulating layers and the dielectric layers. A second conductive layer is filled in the second dendriform via. The insulating layers and conductive layers are removed to form a dendriform lower electrode. The dendriform electrode provides a larger surface area to increase capacitance. Further, a polysilicon layer of hemispherical grains is formed to increase the surface area of the lower electrode.

Abstract translation: 提供叠层型电容器的制造方法和结构，包括在半导体衬底上形成具有第一通孔的第一介电层。 第一导电层被填充到第一通孔中。 然后，形成绝缘层和电介质层。 使用光刻步骤在绝缘层和电介质层中形成第二树状通道。 第二导电层填充在第二树状通孔中。 去除绝缘层和导电层以形成树状下电极。 树状电极提供更大的表面积以增加电容。 此外，形成半球状晶粒的多晶硅层以增加下电极的表面积。

公开(公告)号：US06429135B1

公开(公告)日：2002-08-06

申请号：US09754354

申请日：2001-01-05

Applicant: Horng-Nan Chern ,  Kun-Chi Lin

Inventor： Horng-Nan Chern ,  Kun-Chi Lin

IPC: H01L21302

CPC classification number: H01L21/823425 ,  H01L21/28247 ,  H01L21/76829 ,  H01L21/76837 ,  H01L21/823468

Abstract: The semiconductor wafer includes a substrate, a gate positioned on the substrate, a cap layer positioned on top of the gate, and a silicon oxide spacer positioned around both the gate and the cap layer. Firstly, a dielectric layer is formed on the semiconductor wafer to cover the gate. An etching back process is then performed to remove portions of both the dielectric layer and the silicon oxide spacer. Finally, a silicon nitride spacer is formed on the dielectric layer around the cap layer. The silicon nitride spacer is positioned on the surface of the dielectric layer and functions in reducing stress between the silicon nitride spacer and the substrate.

Abstract translation: 半导体晶片包括衬底，位于衬底上的栅极，位于栅极顶部的覆盖层和位于栅极和盖层两侧的氧化硅间隔物。 首先，在半导体晶片上形成介电层以覆盖栅极。 然后进行蚀刻反应处理以去除电介质层和氧化硅间隔物的部分。 最后，在覆盖层周围的电介质层上形成氮化硅间隔物。 氮化硅间隔物定位在电介质层的表面上，起减少氮化硅间隔物和衬底之间的应力的作用。

公开(公告)号：US06255229B1

公开(公告)日：2001-07-03

申请号：US09074780

申请日：1998-05-08

Applicant: Kevin Lin ,  Horng-Nan Chern ,  Kun-Chi Lin

Inventor： Kevin Lin ,  Horng-Nan Chern ,  Kun-Chi Lin

IPC: H01L21469

CPC classification number: H01L21/0214 ,  H01L21/02129 ,  H01L21/02271 ,  H01L21/02362 ,  H01L21/3145 ,  H01L21/31625 ,  H01L21/76801

Abstract: A method for forming a semiconductor dielectric layer comprising the steps of providing a substrate having a plurality of semiconductor devices already formed thereon, and then forming a first dielectric layer over the substrate. Next, a silicon oxy-nitride layer is formed over the first dielectric layer, and finally a second dielectric layer is formed over the silicon oxy-nitride layer.

Abstract translation: 一种形成半导体电介质层的方法，包括以下步骤：提供其上已经形成有多个半导体器件的衬底，然后在衬底上形成第一电介质层。 接下来，在第一介电层上形成氮氧化硅层，最后在氮氧化硅层上形成第二电介质层。

公开(公告)号：US6140202A

公开(公告)日：2000-10-31

申请号：US208739

申请日：1998-12-08

Applicant: Horng-Nan Chern ,  Kun-Chi Lin

Inventor： Horng-Nan Chern ,  Kun-Chi Lin

IPC: H01L21/02 ,  H01L21/3213 ,  H01L21/8242

CPC classification number: H01L28/92 ,  H01L21/32139 ,  H01L27/10852

Abstract: A method for fabricating a double-cylinder capacitor is provided. The double-cylinder capacitor has a storage electrode having dual, concentric cylinder structures. The dielectric layer and the top electrode are formed in sequence over the bottom electrode. The storage area is thus enlarged by the double-cylinder capacitor of the invention. Thus, the capacitance of the capacitor can be effectively increased.

Abstract translation: 提供一种制造双缸电容器的方法。 双缸电容器具有具有双重同心圆筒结构的存储电极。 电介质层和顶电极依次形成在底电极上。 因此，通过本发明的双缸电容器来扩大存储区域。 因此，可以有效地增加电容器的电容。

公开(公告)号：US5963811A

公开(公告)日：1999-10-05

申请号：US906528

申请日：1997-08-05

Applicant: Horng-Nan Chern

Inventor： Horng-Nan Chern

IPC: H01L21/336 ,  H01L29/10

CPC classification number: H01L29/66492 ,  H01L29/6659 ,  H01L29/1083

Abstract: A method of fabricating a MOS device with a localized punchthrough stopper. In the process, a dummy layer is employed to define a well for implanting the localized punchthrough stopper. The dummy layer is preferably made of silicon nitride, which has a high etching selectivity with respect to the oxide material forming sidewall spacers of MOS devices. The localized punchthrough stopper is formed at the boundary of the lightly-doped regions and the channel by implanting impurities through the well resulting from the removal of a portion of the dummy layer adjacent to the gate structure.

Abstract translation: 一种制造具有局部穿通塞的MOS器件的方法。 在该过程中，使用虚拟层来限定用于植入局部穿通止动器的阱。 虚设层优选由氮化硅制成，其相对于形成MOS器件的侧壁间隔物的氧化物材料具有高蚀刻选择性。 局部穿通止动器通过从邻近栅极结构去除一部分虚设层而产生的阱通过注入杂质形成在轻掺杂区域和沟道的边界处。

公开(公告)号：US6159806A

公开(公告)日：2000-12-12

申请号：US473985

申请日：1999-12-29

Applicant: Horng-Nan Chern ,  Hsi-Chia Lin ,  Kun-Chi Lin

Inventor： Horng-Nan Chern ,  Hsi-Chia Lin ,  Kun-Chi Lin

IPC: H01L21/8234

CPC classification number: H01L21/823468

Abstract: A method for depositing an oxide layer after spacer formation is disclosed. Owing to an oxide layer after spacer formation, therefore substantially increasing the effective thickness of spacer of the peripheral circuit. The method includes which includes a substrate on which an interior and a peripheral circuit are defined, wherein there is a gate oxide layer formed on the substrate. Sequentially an interior gate and a peripheral gate are formed. Then, N-type ions are implanted into the substrate of the interior and peripheral circuit. Consequently, conformal a second dielectric layer and a third dielectric layer are deposited above the substrate, interior gate, and peripheral gate, wherein second dielectric layer is etched to form a spacer of the interior gate and the peripheral gate. And then N.sup.+ -type ions are implanted into the substrate to form source/drain by using the peripheral gate, the spacer and a portion of the third dielectric layer that runs along the spacer as a mask. Subsequently, a blanket inter-plasma dielectric is deposited above the substrate. Finally, inter-polysilicon dielectric of the interior and peripheral circuit is etched anisotropically to form a plurality of contacts.

Abstract translation: 公开了一种在间隔物形成之后沉积氧化物层的方法。 由于在间隔物形成之后的氧化物层，因此大大增加了外围电路的间隔物的有效厚度。 该方法包括其中限定了内部和外围电路的衬底，其中在衬底上形成有栅极氧化层。 顺序地形成内部门和外围门。 然后，将N型离子注入到内部和外围电路的衬底中。 因此，在衬底，内部栅极和外围栅极上方沉积第二绝缘层和第三介电层，其中第二介电层被蚀刻以形成内部栅极和外围栅极的间隔物。 然后通过使用外围栅极，间隔物和沿着间隔物延伸作为掩模的第三电介质层的一部分，将N +型离子注入到衬底中以形成源极/漏极。 随后，在衬底上方沉积一层等离子体电介质。 最后，各向异性地蚀刻内部和外围电路的多晶硅间电介质以形成多个触点。

公开(公告)号：US6100158A

公开(公告)日：2000-08-08

申请号：US302884

申请日：1999-04-30

Applicant: Tzung-Han Lee ,  Kun-Chi Lin ,  Horng-Nan Chern ,  Alex Hou

Inventor： Tzung-Han Lee ,  Kun-Chi Lin ,  Horng-Nan Chern ,  Alex Hou

IPC: H01L21/762 ,  H01L21/76

CPC classification number: H01L21/76224

Abstract: A method of manufacturing an alignment mark. A substrate having a device region and an alignment mark region is provided. The device region is higher than the alignment mark region. The device region comprises an active region. An isolation structure is formed in the substrate at the edge of the alignment mark region and a first dielectric layer is formed over a portion of the substrate at the alignment mark region, simultaneously. A conductive layer is formed over the substrate. A portion of the conductive layer is removed to expose the first dielectric layer at the alignment mark region. The remaining conductive layer is patterned to form a component at the active region. A second dielectric layer with a smooth surface is formed over the substrate to cover the component. A wire is formed on the second dielectric layer, wherein a distance between the wire and the alignment mark region is larger than a distance between the component and the alignment mark region.

Abstract translation: 制造对准标记的方法。 提供具有器件区域和对准标记区域的衬底。 器件区域高于对准标记区域。 器件区域包括有源区。 在对准标记区域的边缘处的基板中形成隔离结构，同时在对准标记区域的一部分基板上形成第一电介质层。 导电层形成在衬底上。 去除导电层的一部分以在对准标记区域露出第一介电层。 将剩余的导电层图案化以在有源区域形成部件。 在衬底上形成具有光滑表面的第二电介质层以覆盖该部件。 在第二电介质层上形成导线，其中导线与对准标记区域之间的距离大于部件与对准标记区域之间的距离。

公开(公告)号：US6040241A

公开(公告)日：2000-03-21

申请号：US21750

申请日：1998-02-11

Applicant: Tzung-Han Lee ,  Horng-Nan Chern

Inventor： Tzung-Han Lee ,  Horng-Nan Chern

IPC: H01L21/28 ,  H01L21/768 ,  H01L21/336

CPC classification number: H01L21/76885 ,  H01L21/28061 ,  H01L21/76801

Abstract: The method in the present invention for forming insulation over conductor includes the following steps. At first, a substrate with a first conductor formed over is provided. The first conductor can be either a gate structure or an interconnection layer. A dielectric layer is then formed over the first conductor the substrate. A portion of the dielectric layer is removed for having a recess free sidewall on the dielectric layer around the first conductor. An insulation for succeeding conductive layer is formed.

Abstract translation: 用于形成导体绝缘的本发明中的方法包括以下步骤。 首先，提供形成有第一导体的基板。 第一导体可以是栅极结构或互连层。 然后在衬底的第一导体上形成电介质层。 去除介电层的一部分，以在第一导体周围的介电层上具有无凹槽的侧壁。 形成用于后续导电层的绝缘体。

公开(公告)号：US5981336A

公开(公告)日：1999-11-09

申请号：US999116

申请日：1997-12-29

Applicant: Horng-Nan Chern

Inventor： Horng-Nan Chern

IPC: H01L21/8242 ,  H01L27/108

CPC classification number: H01L27/10852 ,  H01L27/10817

Abstract: A process for forming a double-layer crown capacitor is provided for increasing the surface area of the capacitor and is applied to a memory unit. The process includes: a) forming a contact window, b) forming a first conducting layer, c) forming a second insulator over the first conducting layer, d) forming a second conducting layer, e) forming a third insulator, f) removing portions of the third insulator and the second conducting layer for exposing a part of the second conducting layer to form a masking layer, g) removing another portion of the third insulator and portions of the second insulator and the first conducting layer, h) removing another portion of the second conducting layer and a portion of the second insulator not covered by the masking layer, i) forming spacers alongside the masking layer and another portion of the second insulator, and removing the masking layer and the another portion of the second insulator for defining a first capacitor by the spacers and another portion of the first conducting layer, j) forming a dielectrical layer, and k) forming a third conducting layer to serve as a second capacitor.

Abstract translation: 提供一种形成双层冠状电容器的方法，用于增加电容器的表面积，并施加到存储器单元。 该方法包括：a）形成接触窗，b）形成第一导电层，c）在第一导电层上形成第二绝缘体，d）形成第二导电层，e）形成第三绝缘体，f） 所述第三绝缘体和所述第二导电层用于暴露所述第二导电层的一部分以形成掩模层，g）去除所述第三绝缘体的另一部分和所述第二绝缘体和所述第一导电层的部分，h）去除另一部分 并且所述第二绝缘体的一部分未被所述掩模层覆盖，i）沿着所述掩蔽层和所述第二绝缘体的另一部分形成间隔物，以及去除所述掩蔽层和所述第二绝缘体的另一部分以限定 通过所述间隔物和所述第一导电层的另一部分的第一电容器，j）形成介电层，以及k）形成第三导电层以用作第二电容器。