Output controller for a dot printer head
    31.
    发明授权
    Output controller for a dot printer head 失效
    点打印机头的输出控制器

    公开(公告)号:US5481654A

    公开(公告)日:1996-01-02

    申请号:US923540

    申请日:1992-08-03

    CPC classification number: B41J2/30

    Abstract: A printing mode setting portion outputs energizing time data corresponding to a selected printing mode when selecting the printing mode according to operation of the operation unit. Based on the energizing time data, the energizing time period of a head energizing signal which is output from a head driving portion to a driving coil of a dot printer head is controlled by the energizing time control portion 6. When printing mode having a high dot density is selected, printing energy is reduced and the energizing time period is refined for the driving coil 8, thus making it made possible to lower the noise level.

    Abstract translation: 当根据操作单元的操作选择打印模式时,打印模式设置部分输出与所选打印模式相对应的通电时间数据。 基于通电时间数据,通过激励时间控制部6控制从打印头驱动部向点打印机头的驱动线圈输出的磁头通电信号的通电时间。当具有高点的打印模式 密度被选择,打印能量降低,激励时间段对于驱动线圈8细化,从而使得降低噪声水平成为可能。

    Memory device having backup power supply
    32.
    发明授权
    Memory device having backup power supply 失效
    具有备用电源的存储器件

    公开(公告)号:US4777626A

    公开(公告)日:1988-10-11

    申请号:US807828

    申请日:1985-12-11

    CPC classification number: G06F1/24 G11C5/141 G11C7/22 G11C7/24

    Abstract: A memory device includes a reset signal generator for generating a reset signal when the output voltage from a main power supply circuit to supply a driving voltage to a memory decreases to a first predetermined voltage, and a switching circuit for allowing a data holding voltage from a backup power supply to be supplied to the memory in place of the driving voltage from the main power supply circuit in response to the reset signal. This memory device further includes a comparator for generating an inhibiting signal when it detects that the data holding voltage from the backup power supply following generation of the reset signal is lower than the voltage necessary to hold the data in the memory, and a control circuit for setting the memory into an operation inhibition state when it detects that the inhibiting signal was generated from the comparator following the reset signal.

    Abstract translation: 存储装置包括复位信号发生器,用于当来自主电源电路的输出电压向存储器提供驱动电压时产生复位信号,将其恢复到第一预定电压;以及切换电路,用于允许来自 替代来自主电源电路的驱动电压的备用电源被提供给存储器,以响应于复位信号。 该存储装置还包括一个比较器,用于在检测到复位信号产生之后的备用电源的数据保持电压低于将数据保持在存储器中所需的电压时,产生禁止信号;以及控制电路, 当检测到从复位信号后的比较器产生禁止信号时,将存储器设置为操作禁止状态。

    Dot character display apparatus
    33.
    发明授权
    Dot character display apparatus 失效
    点字显示装置

    公开(公告)号:US4751508A

    公开(公告)日:1988-06-14

    申请号:US820563

    申请日:1986-01-21

    CPC classification number: G09G3/20 G09G5/24

    Abstract: A dot character display apparatus includes a control circuit for transferring data corresponding to character body and upper and lower symbols from first to third character generators to image buffers, a drive circuit for driving a dot matrix display section on the basis of the data stored in the image buffers. The dot matrix display section has an upper display area to display the upper symbol, a central display area to display the charcter body, and a lower display area to display the lower symbol. The drive circuit has a first drive section to drive the central display area of the dot matrix display section in accordance with data indicative of the character body from the first character generator, and a secod drive section to drive the upper and lower display areas of the dot matrix display section in accordance with data representative of the upper and lower symbols from the second and third character generators.

    Abstract translation: 点字显示装置包括:控制电路,用于将与字体相对应的数据和从第一到第三字符发生器的上下符号传送到图像缓冲器;驱动电路,用于根据存储在 图像缓冲区 点阵显示部分具有显示上部符号的上部显示区域,用于显示特征体的中央显示区域和显示较低符号的下部显示区域。 驱动电路具有:第一驱动部,其根据来自第一字符发生器的字符体的数据,驱动点阵显示部的中央显示区域;驱动驱动部,驱动上述显示区域的上下显示区域; 点阵显示部分,根据表示来自第二和第三字符发生器的上部和下部符号的数据。

    METHOD FOR PRODUCING epsilon-CAPROLACTAM AND METHOD FOR PRODUCING PENTASIL TYPE ZEOLITE
    37.
    发明申请
    METHOD FOR PRODUCING epsilon-CAPROLACTAM AND METHOD FOR PRODUCING PENTASIL TYPE ZEOLITE 失效
    生产ε-CAPROLACTAM的方法和生产PENTASIL型沸石的方法

    公开(公告)号:US20100105893A1

    公开(公告)日:2010-04-29

    申请号:US12543022

    申请日:2009-08-18

    CPC classification number: C07D201/04 C01B37/02 C01B39/36 C01B39/40 Y02P20/52

    Abstract: The present invention provides a method which can produce ε-caprolactam with a good selectivity by reacting cyclohexanone oxime with a good conversion in a vapor phase Beckmann rearrangement reaction. Disclosed is a method for producing ε-caprolactam, which comprises performing a vapor phase Beckmann rearrangement reaction of cyclohexanone oxime in the presence of a pentasil type zeolite, wherein the pentasil type zeolite is a zeolite obtained by subjecting a mixture containing a silicon compound, water, and a compound represented by formula (I): [(R1)3N+—(CH2)m—N+(R1)2—(CH2)m—N+(R1)3]·3/n (A)   (I) wherein R1 represents an alkyl group having 1 to 4 carbon atoms, A represents an n-valent anion, m represents an integer of 5 to 7, and n represents an integer of 1 to 3, to a hydrothermal synthesis reaction.

    Abstract translation: 本发明提供了一种通过在气相贝克曼重排反应中使环己酮肟与良好的转化率反应,能够以良好的选择性生产“己内酰胺”的方法。 公开了一种生产ε-己内酰胺的方法,其包括在pentasil型沸石存在下进行环己酮肟的气相Beckmann重排反应,其中pentasil型沸石是通过使含有硅化合物的混合物, 水和由式(I)表示的化合物:[(R1)3N + - (CH2)m-N +(R1)2-(CH2)m-N +(R1)3]·3 / n(A) 其中,R1表示碳原子数1〜4的烷基,A表示n价阴离子,m表示5〜7的整数,n表示1〜3的整数。

    Connecting structure for connecting a memory unit to a memory unit
controller
    38.
    发明授权
    Connecting structure for connecting a memory unit to a memory unit controller 失效
    将存储单元连接到存储单元控制器的连接结构

    公开(公告)号:US4849944A

    公开(公告)日:1989-07-18

    申请号:US85187

    申请日:1987-08-14

    Abstract: Grounding terminals of a memory unit are disposed at the opposite ends of an array of signal terminals of the memory unit, respectively, reception grounding terminals of a connector are disposed at the opposite ends of any array of reception signal terminals of the connector, respectively, the grounding terminals of the memory unit are connected to the reception grounding terminals of the connector, respectively, before the signal terminals of the memory unit are connected to the reception signal terminals of the connector in inserting the memory unit in the connector. Upon the insertion of the memory unit in the connector, the static electricity accumulate in the memory unit is discharged surely to a ground without affecting the semiconductor memory of the memory unit through the signal terminals and the reception signal terminals.

    Abstract translation: 存储器单元的接地端子分别设置在存储器单元的信号端子阵列的相对端,连接器的接收接地端子分别设置在连接器的接收信号端子的任何阵列的相对端, 在将存储单元插入连接器中之前,存储单元的接地端分别连接到连接器的接收接地端子,在存储器单元的信号端子连接到连接器的接收信号端子之前。 在将存储器单元插入连接器中时,存储单元中积聚的静电通过信号端子和接收信号端子不会影响存储器单元的半导体存储器而确实地放电到地面。

    Stepping motor driving circuit
    39.
    发明授权
    Stepping motor driving circuit 失效
    步进电机驱动电路

    公开(公告)号:US4486696A

    公开(公告)日:1984-12-04

    申请号:US508066

    申请日:1983-06-24

    CPC classification number: H02P8/24

    Abstract: A stepping motor driving circuit includes a plurality of switching transistors having their emitter-collector paths connected to the corresponding ends of motor coils, a plurality of diodes having their anodes connected to the above-mentioned ends of the motor coils and their cathodes connected to a common terminal, and a braking circuit connected between the cathode of the diodes and the other end of the motor coils, in which the switching transistors are sequentially turned ON to permit excitation currents to pass through the corresponding motor coils. The braking circuit has a variable effective impedance.

    Abstract translation: 步进电机驱动电路包括多个开关晶体管,其发射极 - 集电极路径连接到电动机线圈的相应端,多个二极管的阳极连接到电动机线圈的上述端部,并且其阴极连接到 公共端子和连接在二极管的阴极和电动机线圈的另一端之间的制动电路,其中开关晶体管顺序地导通,以允许激励电流通过相应的电动机线圈。 制动电路具有可变的有效阻抗。

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