公开(公告)号：US20110109380A1

公开(公告)日：2011-05-12

申请号：US12617428

申请日：2009-11-12

Applicant: Sunghyun Park ,  Xiaoyong Li ,  Tzu-wang Pan

Inventor： Sunghyun Park ,  Xiaoyong Li ,  Tzu-wang Pan

IPC: H03B1/00

CPC classification number: H03H11/126

Abstract: An active analog filter (700, 1000) having a MOS capacitor device (730, 1030) with improved linearity is proposed. In an exemplary embodiment, dc bias voltage sources (755, 745) alter the capacitance of MOS varactors (740, 750) connected in anti parallel so that the total capacitance of the MOS capacitor device remains constant or within a range over the voltage range of the filter and the filter linearity is set. In a further exemplary embodiment the output stage (1070) of the operational amplifier circuit (1020) of the active analog filter (1000) is modified so that the dc bias voltage is provided by resistors (1055, 1045) connected to a current source (1060) already existing in the filter. Thus the linearity is set and the die area is significantly reduced.

Abstract translation: 提出了一种具有提高线性度的MOS电容器件（730,1030）的有源模拟滤波器（700,1000）。 在示例性实施例中，直流偏置电压源（755,745）改变以反并联方式连接的MOS可变电抗器（740,750）的电容，使得MOS电容器装置的总电容保持恒定或超过电压范围 滤波器和滤波器线性度被设置。 在另一示例性实施例中，有源模拟滤波器（1000）的运算放大器电路（1020）的输出级（1070）被修改，使得直流偏置电压由连接到电流源的电阻（1055,1045） 1060）已经存在于过滤器中。 因此，设置线性度并且模具面积显着减小。

公开(公告)号：US5917859A

公开(公告)日：1999-06-29

申请号：US893863

申请日：1997-07-11

Applicant: Richard G. Yamasaki ,  Tzu-Wang Pan

Inventor： Richard G. Yamasaki ,  Tzu-Wang Pan

IPC: G11B20/14 ,  G11B20/10 ,  G11B20/18 ,  H03L7/06 ,  H04L25/08 ,  H04L25/497 ,  H04L27/28 ,  H04L5/12

CPC classification number: G11B20/10009

Abstract: An improved Viterbi detector for use in a partial-response maximum-likelihood (PRML) channel. The present invention reduces the amount of hardware necessary in the conventional digital implementation, as well as increasing the speed of the system, by utilizing analog circuits. Whereas prior art analog implementations use more complex hardware and less efficient algorithms, the present invention utilizes easily realizable circuitry to perform a more efficient algorithm. A sampled data Viterbi detector compares a sampled analog input signal with two threshold signals. The binary outputs of the comparing means are then provided to a survival sequence register, as well as being used to formulate new threshold signals for the subsequent input sample. The hardware implements Ferguson's method for calculating sequence metrics by representing the accumulated metric difference as two threshold signals. Probability based decisions are then performed in analog comparators. Because Ferguson's method only requires formulation of the difference between metrics rather than formulation of the true metrics themselves, the successive threshold signals that represent this difference can be generated using multi-input track and hold circuits and a voltage summing means.

Abstract translation: 用于部分响应最大似然（PRML）信道的改进的维特比检测器。 本发明通过利用模拟电路来减少传统数字实现中所需的硬件数量以及增加系统的速度。 而现有技术的模拟实现使用更复杂的硬件和较低效率的算法，本发明利用易于实现的电路来执行更有效的算法。 采样数据维特比检测器将采样的模拟输入信号与两个阈值信号进行比较。 然后将比较装置的二进制输出提供给生存序列寄存器，以及用于为随后的输入样本制定新的阈值信号。 硬件通过将累积度量差表示为两个阈值信号来实现Ferguson的计算顺序度量的方法。 然后在模拟比较器中执行基于概率的决策。 因为弗格森的方法只需要制定度量之间的差异，而不是制定真实度量本身，所以可以使用多输入跟踪和保持电路以及电压求和装置来产生代表该差异的连续阈值信号。

公开(公告)号：US5808573A

公开(公告)日：1998-09-15

申请号：US695327

申请日：1996-08-01

Applicant: Shih-Ming Shih ,  Tzu-Wang Pan ,  Jenn-Gang Chern

Inventor： Shih-Ming Shih ,  Tzu-Wang Pan ,  Jenn-Gang Chern

IPC: G11B20/14 ,  H03M1/08 ,  H03M1/12 ,  H04L7/04 ,  H03M1/00

CPC classification number: G11B20/10055 ,  G11B20/1403 ,  H03M1/0836 ,  H03M1/12 ,  H04L7/046

Abstract: Analog-to-digital converter (ADC) output bits are partitioned in a way that simplifies the phase error calculations. The circuit architecture embeds the implementation of the phase error calculations in the analog-to digital-converter (ADC) to simplify the overall circuit implementation. Simplification of the phase error calculations allows a reduction in the complexity of the circuits needed to implement the phase-locked-loop (PLL) for recovering the sampling clock.

Abstract translation: 模数转换器（ADC）输出位以简化相位误差计算的方式进行分区。 电路架构将相位误差计算的实现嵌入在模数转换器（ADC）中，以简化总体电路实现。 相位误差计算的简化可以降低实现锁相环（PLL）所需的电路的复杂性，以恢复采样时钟。