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    Data Object Profiling During Program Execution
    31.
    发明申请
    Data Object Profiling During Program Execution 失效
    程序执行期间的数据对象分析

    公开(公告)号：US20130067192A1

    公开(公告)日：2013-03-14

    申请号：US13230859

    申请日：2011-09-13

    Applicant: Yaakov Yaari

    Inventor： Yaakov Yaari

    IPC: G06F12/02

    CPC classification number: G06F11/3471 ,  G06F12/0292

    Abstract: Systems and methods for identifying objects generated during program execution are provided. In one embodiment, the method comprises examining one or more data structures that include information about allocation of memory space to one or more objects; determining address space allocated to at least one of said objects based on examining said data structure; populating a reverse object map based on the examining of the one or more data structures and the determining of the address space allocated to said objects, such that one or more addresses in memory are associated with an object instantiated during program execution; and determining identity of a target object accessed during program execution in association with a respective address, in response to evaluating the respective address against the reverse object map to find the target object.

    Abstract translation: 提供了用于识别在程序执行期间生成的对象的系统和方法。 在一个实施例中，该方法包括检查包括关于向一个或多个对象分配存储器空间的信息的一个或多个数据结构; 基于检查所述数据结构确定分配给所述对象中的至少一个的地址空间; 基于对所述一个或多个数据结构的检查和确定分配给所述对象的地址空间来填充反向对象图，使得存储器中的一个或多个地址与在程序执行期间被实例化的对象相关联; 以及响应于针对所述反向对象图评估相应地址以找到所述目标对象，确定与相应地址相关联的在程序执行期间访问的目标对象的身份。

    Packing two packed signed data in registers with saturation
    32.
    发明授权
    Packing two packed signed data in registers with saturation 失效
    在饱和的寄存器中打包两个打包的签名数据

    公开(公告)号：US08190867B2

    公开(公告)日：2012-05-29

    申请号：US13108723

    申请日：2011-05-16

    Applicant: Alexander Peleg ,  Yaakov Yaari ,  Millind Mittal ,  Larry M. Mennemeier ,  Benny Eitan

    Inventor： Alexander Peleg ,  Yaakov Yaari ,  Millind Mittal ,  Larry M. Mennemeier ,  Benny Eitan

    IPC: G06F9/315

    CPC classification number: G06F9/30036 ,  G06F7/49921 ,  G06F9/30025 ,  G06F9/30032 ,  G06F9/30109 ,  G06F9/3013 ,  G06F9/30145 ,  G06F9/30149 ,  G06F9/30167 ,  G06F9/30181 ,  G06F9/30192 ,  G06F9/30196

    Abstract: A processor comprising a register file, and a decoder to decode an instruction to specify a first source register having a first packed signed 16-bit integers, and to specify a second source register having a second packed signed 16-bit integers. A functional unit to generate a result to be stored in a specified destination. The result including a third packed 8-bit integers including an integer for each integer in the first packed integers, and an integer for each integer in the second packed integers. The integers corresponding to the first packed integers next to one another in the result. The integers corresponding to the second packed integers next to one another. A highest order integer of the result corresponding to a highest order integer of the first packed integers. A lowest order integer of the result corresponding to a lowest order integer of the second packed integers.

    Abstract translation: 一种处理器，包括寄存器文件和解码器，用于解码指定第一源寄存器的指令，该第一源寄存器具有第一打包符号的16位整数，并且指定具有第二打包符号的16位整数的第二源寄存器。 用于生成要存储在指定目的地中的结果的功能单元。 结果包括第三个打包的8位整数，包括第一个打包整数中的每个整数的整数，以及第二个打包整数中的每个整数的整数。 对应于结果中彼此相邻的第一个打包整数的整数。 对应于彼此相邻的第二个打包整数的整数。 结果的最高阶整数对应于第一个打包整数的最高阶整数。 结果的最低阶整数对应于第二个打包整数的最低阶整数。

    SEARCHING WITHIN LOG FILES
    33.
    发明申请
    SEARCHING WITHIN LOG FILES 审中-公开
    在日志文件中搜索

    公开(公告)号：US20120078925A1

    公开(公告)日：2012-03-29

    申请号：US12890755

    申请日：2010-09-27

    Applicant: Noam Behar ,  Oma Raz-Pelleg ,  Moran Shochat ,  Yaakov Yaari ,  Aviad Zlotnick

    Inventor： Noam Behar ,  Oma Raz-Pelleg ,  Moran Shochat ,  Yaakov Yaari ,  Aviad Zlotnick

    IPC: G06F17/30

    CPC classification number: G06F16/3341

    Abstract: A search tool may search a text file for entries matching one or more search criterions. The search tool may parse the file into entries. Entries may be parsed into lines and fields. A search criterion may define possible content in two or more fields and relationship between the two or more fields. The search criterion may be defined based on an exemplary entry of the text file, such as for example based on a selection of fields of the exemplary entry by a user.

    Abstract translation: 搜索工具可以在文本文件中搜索匹配一个或多个搜索准则的条目。 搜索工具可以将文件解析成条目。 条目可能会被分析成行和字段。 搜索条件可以在两个或更多个字段中定义可能的内容以及两个或更多个字段之间的关系。 搜索标准可以基于文本文件的示例性条目来定义，例如基于用户对示例性条目的字段的选择。

    METHOD FOR VALIDATION OF BINARY CODE TRANSFORMATIONS
    34.
    发明申请
    METHOD FOR VALIDATION OF BINARY CODE TRANSFORMATIONS 审中-公开
    用于验证二进制码转换的方法

    公开(公告)号：US20090133005A1

    公开(公告)日：2009-05-21

    申请号：US12206578

    申请日：2008-09-08

    Applicant: Yaakov Yaari

    Inventor： Yaakov Yaari

    IPC: G06F9/45

    CPC classification number: G06F8/443 ,  G06F8/75

    Abstract: A method of validating binary code transformation in one aspect includes analyzing original program and transform program. Control flow graphs are generated for both programs. The two graphs are traversed to create respective linear invariant representations. The linear representations are compared to identify incorrect transformations.

    Abstract translation: 一方面验证二进制码变换的方法包括分析原始程序和变换程序。 生成两个程序的控制流程图。 遍历两个图形以创建相应的线性不变量表示。 比较线性表示以识别不正确的变换。

    Processor executing unpack instruction to interleave data elements from two packed data
    36.
    发明授权
    Processor executing unpack instruction to interleave data elements from two packed data 有权
    处理器执行解包指令来交织来自两个打包数据的数据元素

    公开(公告)号：US06516406B1

    公开(公告)日：2003-02-04

    申请号：US09657448

    申请日：2000-09-08

    Applicant: Alexander Peleg ,  Yaakov Yaari ,  Millind Mittal ,  Larry M. Mennemeier ,  Benny Eitan

    Inventor： Alexander Peleg ,  Yaakov Yaari ,  Millind Mittal ,  Larry M. Mennemeier ,  Benny Eitan

    IPC: G06F9315

    CPC classification number: G06F9/30036 ,  G06F7/49921 ,  G06F9/30025 ,  G06F9/30032 ,  G06F9/30109 ,  G06F9/3013 ,  G06F9/30145 ,  G06F9/30149 ,  G06F9/30167 ,  G06F9/30181 ,  G06F9/30192 ,  G06F9/30196

    Abstract: An apparatus includes an instruction decoder, first and second source registers and a circuit coupled to the decoder to receive packed data from the source registers and to unpack the packed data responsive to an unpack instruction received by the decoder. A first packed data element and a third packed data element are received from the first source register. A second packed data element and a fourth packed data element are received from the second source register. The circuit copies the packed data elements into a destination register resulting with the second packed data element adjacent to the first packed data element, the third packed data element adjacent to the second packed data element, and the fourth packed data element adjacent to the third packed data element.

    Abstract translation: 一种装置包括指令解码器，第一和第二源寄存器以及耦合到解码器的电路，用于从源寄存器接收压缩数据，并根据解码器接收到的解包指令对打包数据进行解包。 从第一源寄存器接收第一打包数据元素和第三打包数据元素。 从第二源寄存器接收第二打包数据元素和第四打包数据元素。 所述电路将打包的数据元素复制到目的地寄存器中，其中与第一打包数据元素相邻的第二打包数据元素，与第二打包数据元素相邻的第三打包数据元素以及与第三打包数据元素相邻的第四打包数据元素 数据元素。

    Microprocessor capable of unpacking packed data in response to a unpack instruction
    37.
    发明授权
    Microprocessor capable of unpacking packed data in response to a unpack instruction 有权
    微处理器能够解包打包数据以响应打包指令

    公开(公告)号：US6119216A

    公开(公告)日：2000-09-12

    申请号：US974435

    申请日：1999-03-22

    Applicant: Alexander Peleg ,  Yaakov Yaari ,  Millind Mittal ,  Larry M. Mennemeier ,  Benny Eitan

    Inventor： Alexander Peleg ,  Yaakov Yaari ,  Millind Mittal ,  Larry M. Mennemeier ,  Benny Eitan

    IPC: G06F9/30 ,  G06F9/302 ,  G06F9/315 ,  G06F9/318

    CPC classification number: G06F9/30036 ,  G06F9/30025 ,  G06F9/30032 ,  G06F9/30109 ,  G06F9/3013 ,  G06F9/30145 ,  G06F9/30149 ,  G06F9/30167 ,  G06F9/30181 ,  G06F9/30196 ,  G06F7/49921

    Abstract: A microprocessor capable of unpacking packed data in response to an unpack instruction. The microprocessor having a a storage area to store a first packed data and a second packed data respectively including a first plurality of data elements and a second plurality of data elements, wherein each data element in the first plurality of data elements corresponds to a different data element in the second plurality of data elements, in a respective position. The microprocessor also includes a circuit that simultaneously copies less than all data elements from the first plurality of data elements and corresponding data elements from the second plurality of data elements into a storage area as a third plurality of separate data elements in a third packed data in response to the unpack instruction.

    Abstract translation: 一个微处理器能够根据打包指令解包打包数据。 所述微处理器具有存储区域以存储第一打包数据和分别包括第一多个数据元素和第二多个数据元素的第二打包数据，其中所述第一多个数据元素中的每个数据元素对应于不同的数据元素 在第二多个数据元素中，处于相应的位置。 微处理器还包括一个电路，其同时将来自第一多个数据元素的所有数据元素和来自第二多个数据元素的相应数据元素少于多个第三数据元素中的第三个数据元素复制到存储区域中， 对打包指令的响应。

    Processor for performing shift operations on packed data
    39.
    发明授权
    Processor for performing shift operations on packed data 失效
    用于对打包数据执行移位操作的处理器

    公开(公告)号：US5818739A

    公开(公告)日：1998-10-06

    申请号：US840245

    申请日：1997-04-17

    Applicant: Alexander Peleg ,  Yaakov Yaari ,  Millind Mittal ,  Larry M. Mennemeier ,  Benny Eitan

    Inventor： Alexander Peleg ,  Yaakov Yaari ,  Millind Mittal ,  Larry M. Mennemeier ,  Benny Eitan

    IPC: G06F7/00 ,  G06F5/01 ,  G06F7/76 ,  G06F9/30 ,  G06F9/315 ,  G06F9/38

    CPC classification number: G06F7/76 ,  G06F9/30025 ,  G06F9/30032 ,  G06F9/30036 ,  G06F9/30167

    Abstract: A processor. The processor includes a decoder being coupled to receive a control signal. The control signal has a first source address, a second source address, a destination address, and an operation field. The first source address corresponds to a fist location. The second source address corresponds to a second location. The destination address corresponds to a third location. The operation field indicates that a type of packed data shift operation is to be performed. The processor further includes a circuit being coupled to the decoder. The circuit is for shifting a first packed data being stored at the first location by a value being stored at the second location. The circuit is further for communicating a corresponding result packed data to the third location.

    Abstract translation: 处理器 处理器包括被耦合以接收控制信号的解码器。 控制信号具有第一源地址，第二源地址，目的地地址和操作字段。 第一个源地址对应于第一个位置。 第二源地址对应于第二位置。 目的地址对应于第三个位置。 操作字段指示将执行一种打包数据移位操作。 处理器还包括耦合到解码器的电路。 电路用于将存储在第一位置的第一打包数据移位存储在第二位置的值。 电路还用于将相应的结果打包数据传送到第三位置。

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