公开(公告)号：US20120149159A1

公开(公告)日：2012-06-14

申请号：US13397865

申请日：2012-02-16

Applicant: Yaocheng Liu ,  Dureseti Chidambarrao ,  Oleg Gluschenkov ,  Judson R. Holt ,  Renee T. Mo ,  Kern Rim

Inventor： Yaocheng Liu ,  Dureseti Chidambarrao ,  Oleg Gluschenkov ,  Judson R. Holt ,  Renee T. Mo ,  Kern Rim

IPC: H01L21/8238

CPC classification number: H01L21/823864 ,  H01L21/76886 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/84 ,  H01L27/1203 ,  H01L27/3279 ,  H01L29/165 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7848

Abstract: While embedded silicon germanium alloy and silicon carbon alloy provide many useful applications, especially for enhancing the mobility of MOSFETs through stress engineering, formation of alloyed silicide on these surfaces degrades device performance. The present invention provides structures and methods for providing unalloyed silicide on such silicon alloy surfaces placed on semiconductor substrates. This enables the formation of low resistance contacts for both mobility enhanced PFETs with embedded SiGe and mobility enhanced NFETs with embedded Si:C on the same semiconductor substrate. Furthermore, this invention provides methods for thick epitaxial silicon alloy, especially thick epitaxial Si:C alloy, above the level of the gate dielectric to increase the stress on the channel on the transistor devices.

公开(公告)号：US07714358B2

公开(公告)日：2010-05-11

申请号：US11672599

申请日：2007-02-08

Applicant: Yaocheng Liu ,  Shreesh Narasimha ,  Katsunori Onishi ,  Kern Rim

Inventor： Yaocheng Liu ,  Shreesh Narasimha ,  Katsunori Onishi ,  Kern Rim

IPC: H01L27/092

CPC classification number: H01L27/1203 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/28247 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/84 ,  H01L29/1045 ,  H01L29/1083 ,  H01L29/165 ,  H01L29/6653 ,  H01L29/66636 ,  H01L29/7843 ,  H01L29/7848

Abstract: Disclosed are embodiments of an n-FET structure with silicon carbon S/D regions completely contained inside amorphization regions and with a carbon-free gate electrode. Containing carbon within the amorphization regions, ensures that all of the carbon is substitutional following re-crystallization to maximize the tensile stress imparted on channel region. The gate stack is capped during carbon implantation so the risk of carbon entering the gate stack and degrading the conductivity of the gate polysilicon and/or damaging the gate oxide is essentially eliminated. Thus, the carbon implant regions can be formed deeper. Deeper S/D carbon implants which are completely amorphized and then re-crystallized provide greater tensile stress on the n-FET channel region to further optimize electron mobility. Additionally, the gate electrode is uncapped during the n-type dopant process, so the n-type dopant dose in the gate electrode can be at least great as the dose in the S/D regions.

Abstract translation: 公开了具有完全包含在非晶化区域内和具有无碳栅电极的硅碳S / D区域的n-FET结构的实施方案。 在非晶化区域内含有碳，确保在再结晶后所有碳都是取代的，以最大限度地增加通道区域上施加的拉伸应力。 在碳注入期间，栅极堆叠被封盖，从而基本上消除了碳进入栅极堆叠并降低栅极多晶硅的导电性和/或损坏栅极氧化物的风险。 因此，可以更深地形成碳注入区域。 完全非晶化然后再结晶的深S / D碳植入物在n-FET沟道区域上提供更大的拉伸应力，以进一步优化电子迁移率。 此外，在n型掺杂剂处理期间，栅电极未被封装，因此栅电极中的n型掺杂剂剂量可以至少大于S / D区域中的剂量。

公开(公告)号：US20100112766A1

公开(公告)日：2010-05-06

申请号：US12685027

申请日：2010-01-11

Applicant: Yaocheng Liu ,  Shreesh Narasimha ,  Katsunori Onishi ,  Kern Rim

Inventor： Yaocheng Liu ,  Shreesh Narasimha ,  Katsunori Onishi ,  Kern Rim

IPC: H01L21/8234 ,  H01L21/336

CPC classification number: H01L27/1203 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/28247 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/84 ,  H01L29/1045 ,  H01L29/1083 ,  H01L29/165 ,  H01L29/6653 ,  H01L29/66636 ,  H01L29/7843 ,  H01L29/7848

Abstract: Disclosed are embodiments of an n-FET structure with silicon carbon S/D regions completely contained inside amorphization regions and with a carbon-free gate electrode. Containing carbon within the amorphization regions, ensures that all of the carbon is substitutional following re-crystallization to maximize the tensile stress imparted on channel region. The gate stack is capped during carbon implantation so the risk of carbon entering the gate stack and degrading the conductivity of the gate polysilicon and/or damaging the gate oxide is essentially eliminated. Thus, the carbon implant regions can be formed deeper. Deeper S/D carbon implants which are completely amorphized and then re-crystallized provide greater tensile stress on the n-FET channel region to further optimize electron mobility. Additionally, the gate electrode is uncapped during the n-type dopant process, so the n-type dopant dose in the gate electrode can be at least great as the dose in the S/D regions.

Abstract translation: 公开了具有完全包含在非晶化区域内和具有无碳栅电极的硅碳S / D区域的n-FET结构的实施方案。 在非晶化区域内含有碳，确保在再结晶后所有碳都是取代的，以最大限度地增加通道区域上施加的拉伸应力。 在碳注入期间，栅极堆叠被封盖，从而基本上消除了碳进入栅极堆叠并降低栅极多晶硅的导电性和/或损坏栅极氧化物的风险。 因此，可以更深地形成碳注入区域。 完全非晶化然后再结晶的深S / D碳植入物在n-FET沟道区域上提供更大的拉伸应力，以进一步优化电子迁移率。 此外，在n型掺杂剂处理期间，栅电极未被封装，因此栅电极中的n型掺杂剂剂量可以至少大于S / D区域中的剂量。

公开(公告)号：US07632724B2

公开(公告)日：2009-12-15

申请号：US11673716

申请日：2007-02-12

Applicant: Dureseti Chidambarrao ,  William K. Henson ,  Yaocheng Liu

Inventor： Dureseti Chidambarrao ,  William K. Henson ,  Yaocheng Liu

IPC: H01L21/00

CPC classification number: H01L29/78603 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/7843

Abstract: A method is provided for fabricating a field effect transistor (“FET”) having a channel region in a semiconductor-on-insulator (“SOI”) layer of an SOI substrate. Desirably, in such method, a sacrificial stressed layer is formed to overlie a first portion of an active semiconductor region but not overlie second portion of the active semiconductor region which shares a common boundary with the first portion. After forming trenches in the SOI layer, the SOI substrate is heated with the stressed layer thereon sufficiently to cause the stressed layer to relax, thereby causing the stressed layer to apply a first stress to the first portion and to apply a second stress to the second portion. For example, when the first stress is tensile, the second stress is compressive, or the first stress can be compressive when the second stress is tensile. Desirably, the stressed layer is then removed to expose the first and second portions of the active semiconductor region. Desirably, the field effect transistor (“FET”) is formed to include (i) a source region in the first portion, (ii) a drain region in the first portion, and (iii) a channel region in the second portion.

Abstract translation: 提供一种用于制造在SOI衬底的绝缘体上半导体（“SOI”）层中具有沟道区的场效应晶体管（“FET”）的方法。 理想地，在这种方法中，牺牲应力层形成为覆盖有源半导体区域的第一部分，但不覆盖与第一部分共用共同边界的有源半导体区域的第二部分。 在SOI层中形成沟槽之后，将SOI衬底上的应力层充分加热，使得应力层松弛，从而使应力层对第一部分施加第一应力并向第二部分施加第二应力 一部分。 例如，当第一应力是拉伸时，第二应力是压缩的，或者当第二应力是拉伸时，第一应力可以是压缩的。 理想地，应力层被去除以暴露有源半导体区域的第一和第二部分。 期望地，场效应晶体管（“FET”）形成为包括（i）第一部分中的源极区域，（ii）第一部分中的漏极区域，以及（iii）第二部分中的沟道区域。

公开(公告)号：US20090181508A1

公开(公告)日：2009-07-16

申请号：US12014934

申请日：2008-01-16

Applicant: Judson R. Holt ,  Yaocheng Liu ,  Kern Rim

Inventor： Judson R. Holt ,  Yaocheng Liu ,  Kern Rim

IPC: H01L21/336

CPC classification number: H01L21/26506 ,  H01L21/324 ,  H01L29/165 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/78 ,  H01L29/7848

Abstract: A method forms a gate stack over a channel region of a substrate and then forms disposable spacers on sides of the gate stack. Trenches are then recessed in regions of the substrate not protected by the gate stack and the disposable spacers. Carbon-doped Silicon lattice structures are then formed in the trenches. During the forming of the Carbon-doped Silicon lattice structures Carbon atoms can be positioned in any substitutional sites within the lattice structures. The Carbon-doped Silicon lattice structures are then amorphized by implantation of an amorphizing species. An annealing process then recrystallizes the amorphized regions by solid-phase epitaxy regrowth to form the source and drain regions. During the annealing, a majority of Carbon atoms are substitutionally incorporated into a Silicon lattice of the source and drain regions to provide tensile stress to the channel region.

Abstract translation: 一种方法在衬底的通道区域上形成栅极堆叠，然后在栅极叠层的侧面上形成一次性间隔物。 沟槽然后凹陷在不被栅极堆叠和一次性间隔件保护的衬底的区域中。 然后在沟槽中形成碳掺杂的硅晶格结构。 在形成碳掺杂硅晶格结构期间，碳原子可以位于晶格结构内的任何取代位置。 然后通过植入非晶化物质将碳掺杂的硅晶格结构非晶化。 退火工艺然后通过固相外延再生长再结晶非晶化区域以形成源区和漏区。 在退火期间，大多数碳原子被替代地并入到源极和漏极区域的硅晶格中，以向沟道区域提供拉伸应力。

公开(公告)号：US20090166770A1

公开(公告)日：2009-07-02

申请号：US11968396

申请日：2008-01-02

Applicant: Oleg Gluschenkov ,  Sameer H. Jain ,  Yaocheng Liu

Inventor： Oleg Gluschenkov ,  Sameer H. Jain ,  Yaocheng Liu

IPC: H01L29/423 ,  H01L21/28

CPC classification number: H01L29/4983 ,  H01L21/268 ,  H01L21/2686 ,  H01L21/2807 ,  H01L21/823828 ,  H01L21/823842

Abstract: A method of fabricating a gate electrode for a gate of a metal oxide semiconductor field effect transistor (MOSFET), where the transistor has a structure incorporating a gate disposed on a substrate. The substrate comprises a source-drain region. The gate includes a gate electrode disposed on a gate dielectric and surrounded by a spacer. The gate electrode includes a capping layer of polysilicon (poly-Si) and a thin polycrystalline intermixed silicon-germanium (SiGe) layer superposed on the gate dielectric. The thin polycrystalline intermixed silicon-germanium (SiGe) layer may be formed by a high-temperature ultrafast melt-crystalization annealing process. The melt-crystallization process of the intermixed silicon-germanium provides an active dopant concentration that reduces the width of a depletion region formed at an interface of the polycrystalline intermixed silicon-germanium (SiGe) layer and the gate dielectric.

Abstract translation: 一种制造用于金属氧化物半导体场效应晶体管（MOSFET）的栅极的栅极的方法，其中晶体管具有结合设置在衬底上的栅极的结构。 衬底包括源极 - 漏极区域。 栅极包括设置在栅极电介质上并被间隔物包围的栅电极。 栅电极包括多晶硅（poly-Si）的覆盖层和叠加在栅极电介质上的薄的多晶混合的硅 - 锗（SiGe）层。 薄多晶混合硅锗（SiGe）层可以通过高温超快熔融结晶退火工艺形成。 混合硅 - 锗的熔融结晶过程提供了活性掺杂剂浓度，其减小了在多晶混合硅 - 锗（SiGe）层和栅极电介质的界面处形成的耗尽区的宽度。

公开(公告)号：US07524740B1

公开(公告)日：2009-04-28

申请号：US12108917

申请日：2008-04-24

Applicant: Yaocheng Liu ,  Devendra Kumar Sadana ,  Kern Rim

Inventor： Yaocheng Liu ,  Devendra Kumar Sadana ,  Kern Rim

IPC: H01L21/36 ,  H01L21/20

CPC classification number: H01L29/1054 ,  H01L21/02532 ,  H01L21/02664 ,  H01L21/26506 ,  H01L21/84

Abstract: A method of forming a localized region of relaxed Si in a layer of strained Si arranged within a strained silicon directly on insulator (SSDOI) semiconductor substrate is provided by the invention. The strained Si layer is formed on a buried oxide (BOX) layer disposed on a Si substrate base. The method includes depositing a nitride hard mask pattern above a region of the strained Si layer in which enhanced electron mobility is desired, leaving an unmasked region within the strained Si layer, and carrying out various other processing steps to modify and relax the unmasked portion of the strained region. The method includes growing an EPI SiGe region upon the unmasked region using pre-amorphization implantation, and forming a buried amorphous SiGe region in a portion of the EPI SiGe region, and an amorphous Si region, below the amorphous SiGe region. Then, using SPE regrowth, modifying the amorphous SiGe and amorphous Si regions to realize an SPE SiGe region and relaxed SPE Si layer. The SiGe region and the SPE SiGe region are etched, leaving the relaxed SPE Si region above the buried oxide layer. The nitride pattern is stripped.

Abstract translation: 本发明提供了一种在布置在直接绝缘体（SSDOI）半导体衬底的应变硅中的应变Si层中形成弛豫Si局部区域的方法。 应变Si层形成在设置在Si衬底基底上的掩埋氧化物（BOX）层上。 该方法包括在需要增强的电子迁移率的应变Si层的区域之上沉积氮化物硬掩模图案，在应变Si层内留下未掩模的区域，并执行各种其它处理步骤以修饰和松弛未曝光部分 紧张区域。 该方法包括使用预非晶化注入在未掩模区域上生长EPI SiGe区域，以及在非晶SiGe区域的一部分EPI SiGe区域和非晶Si区域内形成掩埋非晶SiGe区域。 然后，使用SPE再生长，改性非晶SiGe和非晶Si区，实现SPE SiGe区和松弛的SPE Si层。 蚀刻SiGe区域和SPE SiGe区域，在掩埋氧化物层上方留下松弛的SPE Si区域。 剥离氮化物图案。

公开(公告)号：US20080248626A1

公开(公告)日：2008-10-09

申请号：US11697102

申请日：2007-04-05

Applicant: Yaocheng Liu ,  Zhijiong Luo ,  Katherine L. Saenger ,  Chun-Yung Sung ,  Rajasekhar Venigalla ,  Haizhou Yin

Inventor： Yaocheng Liu ,  Zhijiong Luo ,  Katherine L. Saenger ,  Chun-Yung Sung ,  Rajasekhar Venigalla ,  Haizhou Yin

IPC: H01L21/762

CPC classification number: H01L21/26506 ,  H01L21/02667 ,  H01L21/187 ,  H01L21/76224

Abstract: A hybrid orientation direct-semiconductor-bond (DSB) substrate with shallow trench isolation (STI) that is self-aligned to recrystallization boundaries is formed by patterning a hard mask layer for STI, a first amorphization implantation into openings in the hard mask layer, lithographic patterning of portions of a top semiconductor layer, a second amorphization implantation into exposed portions of the DSB substrate, recrystallization of the portions of the top semiconductor layer, and formation of STI utilizing the pattern in the hard mask layer. The edges of patterned photoresist for the second amorphization implantation are located within the openings in the patterned hard mask layer. Defective boundary regions formed underneath the openings in the hard mask layer are removed during the formation of STI to provide a leakage path free substrate. Due to elimination of a requirement for increased STI width, device density is increased compared to non-self-aligning process integration schemes.

Abstract translation: 通过将STI的硬掩模层图案化，在硬掩模层的开口中进行第一非晶化注入，形成具有与重结晶边界自对准的浅沟槽隔离（STI）的混合取向直接半导体结合（DSB） 顶部半导体层的部分的平版印刷图案化，第二非晶化注入到DSB衬底的暴露部分中，顶部半导体层的部分的再结晶，以及利用硬掩模层中的图案形成STI。 用于第二非晶化注入的图案化光致抗蚀剂的边缘位于图案化的硬掩模层的开口内。 在形成STI期间去除在硬掩模层中形成在开口下面的有缺陷的边界区域，以提供无泄漏路径的衬底。 由于消除了对于增加的STI宽度的要求，与非自对准工艺集成方案相比，器件密度增加。

公开(公告)号：US20080185636A1

公开(公告)日：2008-08-07

申请号：US11672109

申请日：2007-02-07

Applicant: Zhijiong Luo ,  Yaocheng Liu

Inventor： Zhijiong Luo ,  Yaocheng Liu

IPC: H01L21/336 ,  H01L29/78

CPC classification number: H01L29/66545 ,  H01L29/1083 ,  H01L29/165 ,  H01L29/665 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7834

Abstract: A semiconductor structure and related method for fabrication thereof includes a liner layer interposed between: (1) a pedestal shaped channel region within a semiconductor substrate; and (2) a source region and a drain region within a semiconductor material layer located upon the liner layer and further laterally separated from the pedestal shaped channel region within the semiconductor substrate. The liner layer comprises an active doped silicon carbon material. The semiconductor material layer may comprises a semiconductor material other than a silicon carbon semiconductor material. The semiconductor material layer may alternatively comprise a silicon carbon semiconductor material having an opposite dopant polarity and lower carbon content in comparison with the liner layer. Due to presence of the silicon carbon material, the liner layer inhibits dopant diffusion therefrom into the pedestal shaped channel region. Electrical performance of a field effect device that uses the pedestal shaped channel region is thus enhanced.

Abstract translation: 半导体结构及其相关制造方法包括：衬垫层，介于：（1）半导体衬底内的基座形沟道区; 以及（2）位于衬里层上的半导体材料层内的源极区域和漏极区域，并且与半导体衬底内的基座形状沟道区域进一步横向分离。 衬里层包括有源掺杂硅碳材料。 半导体材料层可以包括除了硅碳半导体材料之外的半导体材料。 可选地，半导体材料层可以包含与衬里层相比具有相反掺杂剂极性和较低碳含量的硅碳半导体材料。 由于存在硅碳材料，衬垫层阻止掺杂剂从其中扩散到基座形沟道区域中。 因此，增强了使用基座形状的通道区域的场效应装置的电气性能。

公开(公告)号：US20080026516A1

公开(公告)日：2008-01-31

申请号：US11459730

申请日：2006-07-25

Applicant: Ashima B. Chakravarti ,  Dureseti Chidambarrao ,  Judson R. Holt ,  Yaocheng Liu ,  Kern Rim

Inventor： Ashima B. Chakravarti ,  Dureseti Chidambarrao ,  Judson R. Holt ,  Yaocheng Liu ,  Kern Rim

IPC: H01L21/8234

CPC classification number: H01L21/823864 ,  H01L21/76224 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823878 ,  H01L29/165 ,  H01L29/66628 ,  H01L29/7843 ,  H01L29/7848

Abstract: An embedded silicon carbon (Si:C) having a substitutional carbon content in excess of one percent in order to effectively increase electron mobility by application of tension to a channel region of an NFET is achieved by overfilling a gap or trench formed by transistor gate structures with Si:C and polishing an etching the Si:C to or below a surface of a raised gate structure in a super-Damascene process, leaving Si:C only in selected regions above the transistor source and drain, even though processes capable of depositing Si:C with sufficiently high substitutional carbon content are inherently non-selective.