公开(公告)号：US20050219451A1

公开(公告)日：2005-10-06

申请号：US11093223

申请日：2005-03-30

Applicant: Yuichi Masutani ,  Shingo Nagano ,  Takkuji Yoshida ,  Nobuaki Ishiga ,  Kazunori Inoue

Inventor： Yuichi Masutani ,  Shingo Nagano ,  Takkuji Yoshida ,  Nobuaki Ishiga ,  Kazunori Inoue

IPC: G02F1/1335 ,  G02F1/1343 ,  G02F1/1362 ,  G02F1/1368

CPC classification number: G02F1/13458 ,  G02F1/133555 ,  G02F1/13439 ,  G02F1/136227

Abstract: The present invention intends to provide a manufacturing method of a semi-transmissive liquid crystal display device in which method a structure and manufacturing process thereof are simplified to enable to reduce the manufacturing cost. In order to achieve the above object, a semi-transmissive liquid crystal display device in the invention has a layer constitution in which a reflective pixel electrode is formed with a second conductive film that constitutes a source electrode, a drain electrode, a source wiring and so on and on an upper layer of the second metal film a transmissive pixel electrode made of a transparent conductive film is formed through the insulating film. A TFT array substrate can be formed through 5 times of photoengraving process.

Abstract translation: 本发明旨在提供一种半透射型液晶显示装置的制造方法，其中简化了其结构和制造方法的方法，从而能够降低制造成本。 为了实现上述目的，本发明的半透射型液晶显示装置具有：反射像素电极形成有构成源电极，漏电极，源极配线的第二导电膜的层结构， 因此在第二金属膜的上层上，通过绝缘膜形成由透明导电膜构成的透射性像素电极。 可以通过5倍的光刻工艺形成TFT阵列基板。

公开(公告)号：US20050151914A1

公开(公告)日：2005-07-14

申请号：US11028059

申请日：2005-01-04

Applicant: Yasunori Niwano ,  Yuichi Masutani ,  Ken Nakashima ,  Yuuzou Oodoi ,  Kazuhiro Kobayashi

Inventor： Yasunori Niwano ,  Yuichi Masutani ,  Ken Nakashima ,  Yuuzou Oodoi ,  Kazuhiro Kobayashi

IPC: G02F1/1343 ,  G02F1/136 ,  G02F1/1362 ,  G02F1/1368

CPC classification number: G02F1/134363 ,  G02F1/136227

Abstract: An IPS liquid crystal displaying apparatus includes: a TFT array substrate, an opposite substrate opposed to the TFT array substrate and liquid crystal interposed between the TFT array substrate and the opposite substrate, wherein the TFT array substrate is composed of a glass substrate, a gate insulating film formed on the glass substrate, a possivation film formed on the gate insulating film, a plurality of scanning lines for transmitting a scanning signal, a plurality of signal lines for transmitting an image signal, a plurality of pixels arranged in grid like pattern by crossing the plurality of scanning lines with the plurality of signal lines, a plurality of TFTs implementing switching operation of the image signal on the basis of the scanning signals, a plurality of driving electrodes connected with the TFT, a plurality of opposite electrodes arranged in such a manner that each of the plurality of opposite electrodes is opposed to each of the driving electrodes, and a plurality of common lines for mutually connecting each of the opposite electrode of one of the plurality of pixels with the other one of the plurality of pixels, wherein the TFT array substrate is formed on the passivation film, the passivation film being different from a layer provided with the driving electrode and the opposite electrode.

公开(公告)号：US06686986B2

公开(公告)日：2004-02-03

申请号：US10200762

申请日：2002-07-24

Applicant: Yasunori Niwano ,  Yuichi Masutani ,  Ken Nakashima ,  Yuuzou Oodoi ,  Kazuhiro Kobayashi

Inventor： Yasunori Niwano ,  Yuichi Masutani ,  Ken Nakashima ,  Yuuzou Oodoi ,  Kazuhiro Kobayashi

IPC: G02F11343

CPC classification number: G02F1/134363 ,  G02F1/136227

Abstract: An IPS liquid crystal displaying apparatus includes: a TFT array substrate, an opposite substrate opposed to the TFT array substrate and liquid crystal interposed between the TFT array substrate and the opposite substrate, wherein the TFT array substrate is composed of a glass substrate, a gate insulating film formed on the glass substrate, a possivation film formed on the gate insulating film, a plurality of scanning lines for transmitting a scanning signal, a plurality of signal lines for transmitting an image signal, a plurality of pixels arranged in grid like pattern by crossing the plurality of scanning lines with the plurality of signal lines, a plurality of TFTs implementing switching operation of the image signal on the basis of the scanning signals, a plurality of driving electrodes connected with the TFT, a plurality of opposite electrodes arranged in such a manner that each of the plurality of opposite electrodes is opposed to each of the driving electrodes, and a plurality of common lines for mutually connecting each of the opposite electrode of one of the plurality of pixels with the other one of the plurality of pixels, wherein the TFT array substrate is formed on the passivation film, the passivation film being different from a layer provided with the driving electrode and the opposite electrode.

Abstract translation: IPS液晶显示装置包括：TFT阵列基板，与TFT阵列基板相对的相对基板和介于TFT阵列基板和相对基板之间的液晶，其中TFT阵列基板由玻璃基板，栅极 形成在玻璃基板上的绝缘膜，形成在栅极绝缘膜上的成膜，用于传输扫描信号的多条扫描线，用于传输图像信号的多条信号线，以格子状排列的多个像素，通过 与多个信号线交叉的多个扫描线，多个TFT，其基于扫描信号实现图像信号的切换操作，多个与TFT连接的驱动电极，多个布置在其上的多个相对电极 多个相对电极中的每一个与每个驱动电极相对的方式，以及多个 用于将多个像素中的一个的相对电极与多个像素中的另一个相互连接的公共线，其中TFT阵列基板形成在钝化膜上，钝化膜不同于设置有多个像素的层 驱动电极和相对电极。

公开(公告)号：US6146930A

公开(公告)日：2000-11-14

申请号：US988001

申请日：1997-12-10

Applicant: Kazuhiro Kobayashi ,  Yuichi Masutani ,  Hiroyuki Murai

Inventor： Kazuhiro Kobayashi ,  Yuichi Masutani ,  Hiroyuki Murai

IPC: H01L21/77 ,  H01L21/84 ,  H01L27/12 ,  H01L29/786 ,  H01L21/336 ,  H01L21/8238

CPC classification number: H01L27/1214 ,  H01L29/78621 ,  H01L29/78627

Abstract: An active-matrix liquid crystal display integrally formed with a driver circuit including: a pair of substrates disposed in opposing relation to each other; and a liquid crystal material sandwiched between the pair of substrates,wherein the pair of substrates includes:a TFT substrate including at least an insulative substrate, source interconnection line and gate interconnection line which are formed in a matrix pattern on the insulative substrate, a thin film transistor provided to each pixel portion for use as a switching element for applying a voltage to a portion of the liquid crystal material which lies at a location where the source interconnection line and the gate interconnection line intersect each other, a pixel electrode connected to a drain electrode of the thin film transistor for supplying a voltage to the liquid crystal material, and a CMOS driver circuit having a CMOS which comprises thin film transistors for supplying an electric signal to the thin film transistor of the pixel portion through the source interconnection line and the gate interconnection line; anda counterpart substrate including an insulative substrate and a counter electrode formed thereon,the thin film transistor provided to the pixel portion being of a first conductivity type and of an offset or LDD structure,at least a first conductivity type thin film transistor of the thin film transistors of the CMOS driver circuit being of an offset or LDD structure.

Abstract translation: 一种与驱动电路一体形成的有源矩阵液晶显示器，包括：一对基板，彼此相对设置; 以及夹在所述一对基板之间的液晶材料，其中，所述一对基板包括：至少在所述绝缘基板上形成为矩阵图案的绝缘基板，源极配线和栅极互连配线的TFT基板，薄型 提供给每个像素部分的薄膜晶体管用作用于向位于源极互连线和栅极互连线彼此相交的位置处的液晶材料的一部分施加电压的开关元件，连接到 用于向液晶材料提供电压的薄膜晶体管的漏极电极以及具有CMOS的CMOS驱动电路，CMOS电路包括用于通过源极互连线向像素部分的薄膜晶体管提供电信号的薄膜晶体管，以及 门互连线; 以及包括形成在其上的绝缘基板和对置电极的对置基板，所述薄膜晶体管设置在所述像素部分上，所述像素部分具有第一导电类型和偏移或LDD结构，所述薄膜晶体管至少具有薄的第一导电型薄膜晶体管 CMOS驱动电路的薄膜晶体管具有偏移或LDD结构。

公开(公告)号：US08451395B2

公开(公告)日：2013-05-28

申请号：US12689575

申请日：2010-01-19

Applicant: Shingo Nagano ,  Yuichi Masutani

Inventor： Shingo Nagano ,  Yuichi Masutani

IPC: G02F1/136 ,  H01L21/00 ,  H01L31/00

CPC classification number: H01L27/124 ,  G02F1/136286 ,  G02F2001/134372 ,  H01L27/1288 ,  H01L29/458

Abstract: A thin-film transistor array substrate includes a source line that is formed above a gate insulating layer covering a gate line, a semiconductor layer that is formed on the gate insulating layer and placed in a substantially whole area below a drain electrode, in a substantially whole area below a source electrode, in a substantially whole area below the source line and in a position opposite to the gate electrode, a pixel electrode that is formed directly on the drain electrode, a transparent conductive pattern that is formed directly on the source electrode and the source line in the same layer as the pixel electrode, and a counter electrode that is formed on an interlayer insulating layer covering the pixel electrode and the transparent conductive pattern and generates a fringe electric field with the pixel electrode.

Abstract translation: 薄膜晶体管阵列基板包括形成在覆盖栅极线的栅极绝缘层上方的源极线，形成在栅极绝缘层上并放置在漏极电极下方的大致整个区域中的半导体层，基本上 在源电极下方的整个区域，在源极线下方的大致整个区域和与栅电极相对的位置，直接形成在漏电极上的像素电极，直接形成在源电极上的透明导电图案 以及与像素电极相同的层中的源极线，以及形成在覆盖像素电极和透明导电图案的层间绝缘层上并与像素电极生成边缘电场的对置电极。

公开(公告)号：US07847290B2

公开(公告)日：2010-12-07

申请号：US12411799

申请日：2009-03-26

Applicant: Yasuyoshi Itoh ,  Yuichi Masutani ,  Masaru Aoki

Inventor： Yasuyoshi Itoh ,  Yuichi Masutani ,  Masaru Aoki

IPC: H01L33/00

CPC classification number: H01L27/1288 ,  H01L27/124 ,  H01L29/66765

Abstract: In forming a thin film transistor using multi-tone exposure, a wiring width of a foundational wiring is 40 μm or less, and a ratio of a wiring width of a foundational wiring in a dense case to a space between adjacent wirings is 1.7, preferably 1.0 or less.

Abstract translation: 在使用多色调曝光形成薄膜晶体管时，基线的布线宽度为40μm以下，致密情况下的基布线的布线宽度与相邻布线之间的间隔的比例为1.7，优选 1.0以下。

公开(公告)号：US20100187532A1

公开(公告)日：2010-07-29

申请号：US12689575

申请日：2010-01-19

Applicant: Shingo Nagano ,  Yuichi Masutani

Inventor： Shingo Nagano ,  Yuichi Masutani

IPC: H01L33/00 ,  H01L31/00

CPC classification number: H01L27/124 ,  G02F1/136286 ,  G02F2001/134372 ,  H01L27/1288 ,  H01L29/458

Abstract: A thin-film transistor array substrate includes a source line that is formed above a gate insulating layer covering a gate line, a semiconductor layer that is formed on the gate insulating layer and placed in a substantially whole area below a drain electrode, in a substantially whole area below a source electrode, in a substantially whole area below the source line and in a position opposite to the gate electrode, a pixel electrode that is formed directly on the drain electrode, a transparent conductive pattern that is formed directly on the source electrode and the source line in the same layer as the pixel electrode, and a counter electrode that is formed on an interlayer insulating layer covering the pixel electrode and the transparent conductive pattern and generates a fringe electric field with the pixel electrode.

Abstract translation: 薄膜晶体管阵列基板包括形成在覆盖栅极线的栅极绝缘层上方的源极线，形成在栅极绝缘层上并放置在漏极电极下方的大致整个区域中的半导体层，基本上 在源电极下方的整个区域，在源极线下方的大致整个区域和与栅电极相对的位置，直接形成在漏电极上的像素电极，直接形成在源电极上的透明导电图案 以及与像素电极相同的层中的源极线，以及形成在覆盖像素电极和透明导电图案的层间绝缘层上并与像素电极生成边缘电场的对置电极。

公开(公告)号：US20090242886A1

公开(公告)日：2009-10-01

申请号：US12411799

申请日：2009-03-26

Applicant: Yasuyoshi Itoh ,  Yuichi Masutani ,  Masaru Aoki

Inventor： Yasuyoshi Itoh ,  Yuichi Masutani ,  Masaru Aoki

IPC: H01L29/04

CPC classification number: H01L27/1288 ,  H01L27/124 ,  H01L29/66765

Abstract: In forming a thin film transistor using multi-tone exposure, a wiring width of a foundational wiring is 40 μm or less, and a ratio of a wiring width of a foundational wiring in a dense case to a space between adjacent wirings is 1.7, preferably 1.0 or less.

Abstract translation: 在使用多色调曝光形成薄膜晶体管时，基线的布线宽度为40μm以下，致密情况下的基布线的布线宽度与相邻布线之间的间隔的比例为1.7，优选 1.0以下。

公开(公告)号：US20080131668A1

公开(公告)日：2008-06-05

申请号：US11943976

申请日：2007-11-21

Applicant: Yuichi MASUTANI ,  Shigeaki Noumi ,  Takeshi Shimamura ,  Masaru Aoki

Inventor： Yuichi MASUTANI ,  Shigeaki Noumi ,  Takeshi Shimamura ,  Masaru Aoki

IPC: B44C1/17 ,  G03C5/00

CPC classification number: G02F1/1362 ,  G02F2201/48 ,  Y10T428/24802

Abstract: An array substrate has regions in which an intermediate resist film thickness is formed and processed by an intermediate exposure amount which does not completely expose a resist, respectively on a drain electrode, source terminal, and a common connection wiring which are made of a second conductive film. Thin film patterns or a common wiring made of a first conductive film is formed in substantially entire regions on the bottom layers of the regions so that the heights from a substrate are substantially the same.

Abstract translation: 阵列基板具有分别在漏极电极，源极端子和公共连接布线上由不是完全暴露抗蚀剂的中间曝光量形成并处理中间抗蚀剂膜厚度的区域，所述漏极电极，源极端子和公共连接布线由第二导电 电影。 在这些区域的底层上的基本上整个区域中形成由第一导电膜制成的薄膜图案或公共布线，使得来自基板的高度基本相同。

公开(公告)号：US07362401B2

公开(公告)日：2008-04-22

申请号：US11028059

申请日：2005-01-04

Applicant: Yasunori Niwano ,  Yuichi Masutani ,  Ken Nakashima ,  Yuuzou Oodoi ,  Kazuhiro Kobayashi

Inventor： Yasunori Niwano ,  Yuichi Masutani ,  Ken Nakashima ,  Yuuzou Oodoi ,  Kazuhiro Kobayashi

IPC: G02F1/1343 ,  G02F1/136 ,  G02F1/1333

CPC classification number: G02F1/134363 ,  G02F1/136227

Abstract: An In Plane Switching (IPS) liquid crystal displaying apparatus includes a TFT array substrate, an opposite substrate opposed to the TFT array substrate and a liquid crystal interposed between the TFT array substrate and the opposite substrate. The TFT array substrate includes a plurality of driving electrodes formed on a passivation film and connected with the plurality of TFTs, a plurality of opposite electrodes formed on the passivation film, each of the plurality of opposite electrodes opposing the respective plurality of driving electrodes, and a plurality of common lines configured to connect each of the plurality of opposite electrodes with each of a plurality of pixels. The TFT array substrate provided with a light shielding formed in such a manner as to superpose one signal line of the plurality of signal lines and one opposite electrode of the plurality of opposite electrodes.

Abstract translation: 平面切换（IPS）液晶显示装置包括TFT阵列基板，与TFT阵列基板相对的相对基板和介于TFT阵列基板和相对基板之间的液晶。 TFT阵列基板包括形成在钝化膜上并与多个TFT连接的多个驱动电极，形成在钝化膜上的多个相对电极，多个相对电极中的每一个与相应的多个驱动电极相对，以及 多条公共线被配置为将多个相对电极中的每一个连接到多个像素中的每一个。 所述TFT阵列基板设置有以将所述多条信号线中的一条信号线和所述多个相对电极的一个相对电极叠加的方式形成的遮光部。