公开(公告)号：US20210111861A1

公开(公告)日：2021-04-15

申请号：US17128720

申请日：2020-12-21

Applicant: Advanced Micro Devices, Inc. ,  ATI Technologies ULC

Inventor： Varun Gupta ,  Milam Paraschou ,  Gerald R. Talbot ,  Gurunath Dollin ,  Damon Tohidi ,  Eric Ian Carpenter ,  Chad S. Gallun ,  Jeffrey Cooper ,  Hanwoo Cho ,  Thomas H. Likens, III ,  Scott F. Dow ,  Michael J. Tresidder

IPC: H04L7/04 ,  H04L7/00

Abstract: Systems, apparatuses, and methods for implementing a deskewing method for a physical layer interface on a multi-chip module are disclosed. A circuit connected to a plurality of communication lanes trains each lane to synchronize a local clock of the lane with a corresponding global clock at a beginning of a timing window. Next, the circuit symbol rotates each lane by a single step responsive to determining that all of the plurality of lanes have an incorrect symbol alignment. Responsive to determining that some but not all of the plurality of lanes have a correct symbol alignment, the circuit symbol rotates lanes which have an incorrect symbol alignment by a single step. When the end of the timing window has been reached, the circuit symbol rotates lanes which have a correct symbol alignment and adjusts a phase of a corresponding global clock to compensate for missed symbol rotations.

公开(公告)号：US10581587B1

公开(公告)日：2020-03-03

申请号：US16397848

申请日：2019-04-29

Applicant: Advanced Micro Devices, Inc. ,  ATI Technologies ULC

Inventor： Varun Gupta ,  Milam Paraschou ,  Gerald R. Talbot ,  Gurunath Dollin ,  Damon Tohidi ,  Eric Ian Carpenter ,  Chad S. Gallun ,  Jeffrey Cooper ,  Hanwoo Cho ,  Thomas H. Likens, III ,  Scott F. Dow ,  Michael J. Tresidder

IPC: H04B17/00 ,  H04L7/04 ,  H04L7/00

Abstract: Systems, apparatuses, and methods for implementing a deskewing method for a physical layer interface on a multi-chip module are disclosed. A circuit connected to a plurality of communication lanes trains each lane to synchronize a local clock of the lane with a corresponding global clock at a beginning of a timing window. Next, the circuit symbol rotates each lane by a single step responsive to determining that all of the plurality of lanes have an incorrect symbol alignment. Responsive to determining that some but not all of the plurality of lanes have a correct symbol alignment, the circuit symbol rotates lanes which have an incorrect symbol alignment by a single step. When the end of the timing window has been reached, the circuit symbol rotates lanes which have a correct symbol alignment and adjusts a phase of a corresponding global clock to compensate for missed symbol rotations.

公开(公告)号：US20190181087A1

公开(公告)日：2019-06-13

申请号：US15836239

申请日：2017-12-08

Applicant: Advanced Micro Devices, Inc.

Inventor： Sanjay Dandia ,  Gerald R. Talbot ,  Mahesh S. Hardikar

IPC: H01L23/522 ,  H01L23/528 ,  H01L23/00

Abstract: An integrated circuit assembly includes an integrated circuit package substrate and a conductive land pad disposed on a surface of the integrated circuit package substrate. The conductive land pad comprises a conductor portion, an isolated conductor portion, and an isolation portion disposed between the conductor portion and the isolated conductor portion. The isolated conductor portion may surround a first side of the conductor portion and a second side of the conductor portion. The isolated conductor portion may surround a portion of a perimeter of the conductor portion. The isolation portion may include a gap between the conductor portion and the isolated conductor portion. The gap may have a width smaller than a radius of an interconnect structure of a receiving structure.

公开(公告)号：US09374080B2

公开(公告)日：2016-06-21

申请号：US14518591

申请日：2014-10-20

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Brian W. Amick ,  Gerald R. Talbot ,  Warren Anderson

IPC: H03K17/22

CPC classification number: H03K17/22

Abstract: A method and apparatus is provided for outputting a reset signal during power-up until two conditions are satisfied. In one embodiment, the method and apparatus includes a voltage detector that provides a first output (“VO1”) when an output voltage of a regulator (“VREG”) exceeds a threshold voltage, thereby satisfying a first condition, a comparator receiving a first input voltage and a second input voltage, the comparator providing a second output (“VO2”) when the first input voltage exceeds the second input voltage, thereby satisfying a second condition, and a release circuit that outputs the reset signal unless the voltage detector provides VO1 while the comparator provides VO2.

Abstract translation: 提供一种方法和装置，用于在上电期间输出复位信号，直到满足两个条件。 在一个实施例中，所述方法和装置包括电压检测器，当调节器的输出电压（“VREG”）超过阈值电压时提供第一输出（“VO1”），从而满足第一条件，比较器接收第一 输入电压和第二输入电压，当第一输入电压超过第二输入电压时，比较器提供第二输出（“VO2”），从而满足第二条件，以及释放电路，输出复位信号，除非电压检测器提供 VO1，而比较器提供VO2。