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公开(公告)号：US20240424398A1
公开(公告)日：2024-12-26
申请号：US18748920
申请日：2024-06-20
Applicant: ADVANCED MICRO DEVICES, INC.
Inventor： Karthik Mohan Kumar , Michael Mantor , Pedro Antonio Pena , Archana Ramalingam
Abstract: Systems and techniques for generating and animating non-player characters (NPCs) within virtual digital environments are provided. Multimodal input data is received that comprises a plurality of input modalities for interaction with an NPC having a set of body features and a set of facial features. The multimodal input data is processed through one or more neural networks to generate animation sequences for both the body features and facial features of the NPC. Generating such animation sequences includes disentangling the multimodal input data to generate substantially disentangled latent representations, combining these representations with the multimodal input data, and using a large-language model (LLM) to generate speech data for the NPC. Further processing using reverse diffusion generates face vertex displacement data and joint trajectory data based on the combined representation and generated speech data. The face vertex displacement data, joint trajectory data, and speech data are used to produce an animated representation of the NPC, which is then provided to environment-specific adapters to animate the NPC within a virtual digital environment.
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公开(公告)号：US11995149B2
公开(公告)日：2024-05-28
申请号：US17125457
申请日：2020-12-17
Applicant: ADVANCED MICRO DEVICES, INC.
Inventor： Sateesh Lagudu , Allen H. Rush , Michael Mantor
CPC classification number: G06F17/16 , G06F9/30098 , G06F15/80
Abstract: A processing system includes a first set and a second set of general-purpose registers (GPRs) and memory access circuitry that fetches nonzero values of a sparse matrix into consecutive slots in the first set. The memory access circuitry also fetches values of an expanded matrix into consecutive slots in the second set of GPRs. The expanded matrix is formed based on values of a vector and locations of the nonzero values in the sparse matrix. The processing system also includes a set of multipliers that concurrently perform multiplication of the nonzero values in slots of the first set of GPRs with the values of the vector in corresponding slots of the second set. Reduced sum circuitry accumulates results from the set of multipliers for rows of the sparse matrix.
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公开(公告)号：US11954782B2
公开(公告)日：2024-04-09
申请号：US17208730
申请日：2021-03-22
Applicant: Advanced Micro Devices, Inc. , ATI Technologies ULC
Inventor： Michael Mantor , Laurent Lefebvre , Mikko Alho , Mika Tuomi , Kiia Kallio
CPC classification number: G06T15/005 , G06T15/04
Abstract: A method, system, and non-transitory computer readable storage medium for rasterizing primitives are disclosed. The method, system, and non-transitory computer readable storage medium includes: generating a primitive batch from a sequence of one or more primitives, wherein the primitive batch includes primitives sorted into one or more row groups based on which row of a plurality of rows each primitive intersects; and processing each row group, the processing for each row group including: identifying one or more primitive column intercepts for each of the one or more primitives in the row group, wherein each combination of primitive column intercept and row identifies a bin; and rasterizing the one or more primitives that intersect the bin.
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公开(公告)号：US20230097562A1
公开(公告)日：2023-03-30
申请号：US17488167
申请日：2021-09-28
Applicant: Advanced Micro Devices, Inc.
Inventor： Konstantin I. Shkurko , Matthäus G. Chajdas , Michael Mantor
Abstract: Described herein is a technique for performing ray tracing operations. The technique includes encountering, at a non-leaf node, a pointer to a bottom-level acceleration structure having one or more delta instances; identifying an index associated with the pointer, wherein the index identifies an instance within the bottom-level acceleration structure; and obtaining data for the instance based on the pointer and the index.
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公开(公告)号：US11409840B2
公开(公告)日：2022-08-09
申请号：US17032314
申请日：2020-09-25
Applicant: ADVANCED MICRO DEVICES, INC.
Inventor： Sateesh Lagudu , Allen H. Rush , Michael Mantor , Arun Vaidyanathan Ananthanarayan , Prasad Nagabhushanamgari
Abstract: An array processor includes processor element arrays distributed in rows and columns. The processor element arrays perform operations on parameter values. The array processor also includes memory interfaces that are dynamically mapped to mutually exclusive subsets of the rows and columns of the processor element arrays based on dimensions of matrices that provide the parameter values to the processor element arrays. In some cases, the processor element arrays are vector arithmetic logic unit (ALU) processors and the memory interfaces are direct memory access (DMA) engines. The rows of the processor element arrays in the subsets are mutually exclusive to the rows in the other subsets and the columns of the processor element arrays in the subsets are mutually exclusive to the columns in the other subsets. The matrices can be symmetric or asymmetric, e.g., one of the matrices can be a vector having a single column.
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Patent Agency Ranking
公开(公告)号：US20210209831A1
公开(公告)日：2021-07-08
申请号：US17208730
申请日：2021-03-22
Applicant: Advanced Micro Devices, Inc. , ATI Technologies ULC
Inventor： Michael Mantor , Laurent Lefebvre , Mikko Alho , Mika Tuomi , Kiia Kallio
Abstract: A method, system, and non-transitory computer readable storage medium for rasterizing primitives are disclosed. The method, system, and non-transitory computer readable storage medium includes: generating a primitive batch from a sequence of one or more primitives, wherein the primitive batch includes primitives sorted into one or more row groups based on which row of a plurality of rows each primitive intersects; and processing each row group, the processing for each row group including: identifying one or more primitive column intercepts for each of the one or more primitives in the row group, wherein each combination of primitive column intercept and row identifies a bin; and rasterizing the one or more primitives that intersect the bin.
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公开(公告)号：US10957094B2
公开(公告)日：2021-03-23
申请号：US15250357
申请日：2016-08-29
Applicant: Advanced Micro Devices, Inc. , ATI Technologies ULC
Inventor： Michael Mantor , Laurent Lefebvre , Mikko Alho , Mika Tuomi , Kiia Kallio
Abstract: A system, method and a computer program product are provided for hybrid rendering with deferred primitive batch binning A primitive batch is generated from a sequence of primitives. Initial bin intercepts are identified for primitives in the primitive batch. A bin for processing is identified. The bin corresponds to a region of a screen space. Pixels of the primitives intercepting the identified bin are processed. Next bin intercepts are identified while the primitives intercepting the identified bin are processed.
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公开(公告)号：US10558499B2
公开(公告)日：2020-02-11
申请号：US15794593
申请日：2017-10-26
Applicant: ADVANCED MICRO DEVICES, INC.
Inventor： Maxim V. Kazakov , Michael Mantor
IPC: G06F9/50
Abstract: Footprints, or resource allocations, of waves within resources that are shared by processor cores in a multithreaded processor are measured concurrently with the waves executing on the processor cores. The footprints are averaged over a time interval. A number of waves are spawned and dispatched for execution in the multithreaded processor based on the average footprint. In some cases, the waves are spawned at a rate that is determined based on the average value of the footprints of waves within the resources. The rate of spawning waves is modified in response to a change in the average value of the footprints of the waves within the resources.
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公开(公告)号：US10134102B2
公开(公告)日：2018-11-20
申请号：US14297290
申请日：2014-06-05
Inventor： Mark Evan Cerny , David Simpson , Jason Scanlin , Michael Mantor
Abstract: A GPU is configured to read and process data produced by a compute shader via the one or more ring buffers and pass the resulting processed data to a vertex shader as input. The GPU is further configured to allow the compute shader and vertex shader to write through a cache. Each ring buffer is configured to synchronize the compute shader and the vertex shader to prevent processed data generated by the compute shader that is written to a particular ring buffer from being overwritten before the data is accessed by the vertex shader. It is emphasized that this abstract is provided to comply with the rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.
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公开(公告)号：US20180314579A1
公开(公告)日：2018-11-01
申请号：US15582443
申请日：2017-04-28
Applicant: Advanced Micro Devices, Inc.
Inventor： Carlos Sampayo , Michael Mantor
CPC classification number: G06F11/1048 , G06F9/3865
Abstract: Techniques for handling memory errors are disclosed. Various memory units of an accelerated processing device (“APD”) include error units for detecting errors in data stored in the memory (e.g., using parity protection or error correcting code). Upon detecting an error considered to be an “initial uncorrectable error,” the error unit triggers transmission of an initial uncorrectable error interrupt (“IUE interrupt”) to a processor. This IUE interrupt includes information identifying the specific memory unit in which the error occurred (and possible other information about the error). A halt interrupt is generated and transmitted to the processor in response to the data having the error being consumed (i.e., used by an operation such as an instruction or command), which causes the APD to halt operations. If the data having the error is not consumed, then the halt interrupt is never generated (that the error occurred may remain logged, however).
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