Abstract:
Methods and apparatus for the scrambling of control symbols. In one embodiment, the control symbols are associated with an HDMI interface, and the methods and apparatus are configured to scramble the symbols to as to mitigate the effects of electromagnetic interference (EMI) created by the transmission of otherwise unscrambled sequences of symbols which may contain significant “clock pattern” or other undesirable artifact.
Abstract:
Methods and apparatus for packing and transporting data within an electronic device. In one embodiment, a consumer electronics device having one or more sensors (e.g., camera sensors) uses modified DisplayPort micro-packets for transmission of RAW format data over one or more lanes of a DisplayPort Main Steam. The RAW data is transported over the one or more lanes by mapping symbol sequences generated from the RAW data based on Y-only data mappings schemes of DisplayPort. A mapping scheme is in one variant selected based on the bits length (e.g., bits per pixel) of the RAW data, in addition to the number of lanes used to transport over the Main Stream. In order for the sink correctly unpack received the micro-packets, the transmitting source transmits Main Stream Attribute (MSA) data packets configured to indicate at least the mapping scheme used.
Abstract:
Methods and apparatus for virtual channel allocation within an electronic device. In one exemplary embodiment, the device is a consumer electronics device having multiple camera sensors uses a modified high-speed protocol (e.g., DisplayPort Multi-Stream Transport (MST) protocol) to process camera data via one or more virtual channels. Unlike traditional solutions which rely on an intelligent source device to manage a network of devices, the present disclosure describes in one aspect a network of nodes internal to a consumer electronic device that is managed by the sink node (i.e., a “smart sink”). Additionally, since the full suite of protocol (e.g., DisplayPort) capabilities are unnecessary for certain design scenarios, certain further disclosed simplifications improve performance for sink nodes having very modest capabilities.
Abstract:
Video data and auxiliary data may be sent between a processor and a display device via a single cable using a link aggregator. As such, the link aggregator may receive a first parallel signal that may include the video data and a second parallel signal that may include auxiliary data from the processor. The link aggregator may then send the first parallel signal and the second parallel signal as an aggregated signal to the display device. Upon receiving the aggregated signal at the display device, the link aggregator may de-aggregate the aggregated signal into the first parallel signal and the second parallel signal. The link aggregator may then send the first parallel signal and the second parallel signal to a timing controller of the display device, such that the timing controller may display the video data using the display device.
Abstract:
Methods and apparatus for the flexible provision of control data within large data structures. In one exemplary embodiment, DisplayPort is modified from its existing 8B/10B line coding to 128B/130B (or 128B/132B). In one embodiment, the 128B/130B (or 128B/132B) block includes: sixteen (16) eight (8) bit command or data symbols and a two (2) bit (or four (4) bit) synchronization header. The synchronization header may provide a fixed reference to the next command symbol (for example, the symbol immediately following the synchronization header). In one variant, each command symbol is split into a first and a second portion, where the first portion identifies a control function (control symbol), and the second portion provides a reference to the next command symbol.
Abstract:
An apparatus for transmitting data across a high-speed serial bus includes an IEEE 802.3-compliant PHY having a GMII interface; an IEEE 1394-compliant PHY in communication with the IEEE 802.3-compliant PHY via a switch; the switch determining whether data transmission is to be routed to the IEEE 802.3-compliant PHY or the IEEE 1394-compliant PHY; a first connection, the first connection for transmitting data between a device and the IEEE 802.3-compliant PHY; and a second connection, the second connection for transmitting data between a device and the IEEE 1394-compliant PHY.
Abstract:
Methods and apparatus for calibration of interface operation of a display device. In one exemplary embodiment of the invention, an embedded DisplayPort (eDP) source element (such as a graphics processing unit (GPU)) configures itself to support the minimum requirements necessary to support a sink element (such as a screen display). Unlike prior art solutions, minimum sink requirements are identified during a calibration process, and the source is configured accordingly. By tailoring the source to the specific requirements of the sink, the device can initialize faster, consume less power, etc. Moreover, in another aspect of the present invention, if a device does not initialize to an expected configuration based on prior calibration settings, the device can be flagged as having faulty or failing components.
Abstract:
Methods and apparatus for estimating received error rates. In one embodiment, the estimation of received error rates is conducted in relation to a bus interface such as a high-speed High-Definition Multimedia Interface (HDMI) interface, and the method utilizes corrupted symbols that violate TMDS symbol rules, the corrupted symbols being easily detected and counted. In one exemplary implementation, a symbol error rate (SER) can be estimated from the number of detected invalid symbols. The SER can be used to diagnose the performance of the HDMI interface, and optionally as a basis for selecting or implementing corrective action(s).
Abstract:
A data communications system is disclosed having at least one Legacy cloud coupled to at least one Beta cloud. The system further having at least one BOSS node and at least one border node. A method for ensuring compatibility is disclosed comprising determining when the BOSS node is idle, determining whether the last packet transmitted by any border node was an Alpha format packet if the BOSS node is idle, and unlocking the Legacy cloud if the last packet transmitted by the border node was not an Alpha format packet.
Abstract:
Methods and apparatus for the flexible provision of control data within large data structures. In one exemplary embodiment, DisplayPort is modified from its existing 8B/10B line coding to 128B/130B (or 128B/132B). In one embodiment, the 128B/130B (or 128B/132B) block includes: sixteen (16) eight (8) bit command or data symbols and a two (2) bit (or four (4) bit) synchronization header. The synchronization header may provide a fixed reference to the next command symbol (for example, the symbol immediately following the synchronization header). In one variant, each command symbol is split into a first and a second portion, where the first portion identifies a control function (control symbol), and the second portion provides a reference to the next command symbol.