公开(公告)号：US20140368521A1

公开(公告)日：2014-12-18

申请号：US14267969

申请日：2014-05-02

Applicant: ARM Limited

Inventor： Anders Lassen ,  Jorn Nystad ,  Alexis Mather ,  Sean Tristram Ellis

IPC: G06T1/60

CPC classification number: G06T1/60 ,  G06T1/20 ,  G06T11/001 ,  G06T11/40 ,  G06T15/005 ,  G09G5/39 ,  G09G2360/122

Abstract: A tile-based graphics processing pipeline comprising a rasteriser 3, a renderer 6, a tile buffer 10 configured to store rendered fragment data locally to the graphics processing pipeline prior to that data being written out to an external memory, a write out stage 13 configured to write data stored in the tile buffer to an external memory, and a programmable processing stage 14. The programmable processing stage 14 is operable under the control of graphics program instructions to read fragment data stored in the tile buffer 10 on a random access basis, perform a processing operation using the read fragment data, and write the result of the processing operation into the tile buffer 10 or to an external memory.

公开(公告)号：US20140354644A1

公开(公告)日：2014-12-04

申请号：US13933612

申请日：2013-07-02

Applicant: ARM Limited

Inventor： Jorn Nystad

IPC: G06T1/20 ,  G06T15/80

CPC classification number: G06T1/20 ,  G06F9/3838 ,  G06F9/3851 ,  G06T15/005 ,  G06T2210/52

Abstract: A data processing system determines for a stream of instructions to be executed, whether there are any instructions that can be re-ordered in the instruction stream 41 and assigns each such instruction to an instruction completion tracker and includes in the encoding for the instruction an indication of the instruction completion tracker it has been assigned to 42. For each instruction in the instruction stream, an indication of which instruction completion trackers, if any, the instruction depends on is also provided 43, 44. Then, when an instruction that is indicated as being dependent on an instruction completion tracker is to be executed, the status of the relevant instruction completion tracker is checked before executing the instruction.

Abstract translation: 数据处理系统确定要执行的指令流，是否存在可以在指令流41中重新排序的任何指令，并将每个这样的指令分配给指令完成跟踪器，并且在指令的编码中包括指示 指令完成跟踪器已被分配给42.对于指令流中的每个指令，还提供指示依赖于哪个指令完成跟踪器（如果有的话）的指示43,44。然后，当指示指令 由于依赖于执行指令完成跟踪器，所以在执行指令之前检查相关指令完成跟踪器的状态。

公开(公告)号：US20140327688A1

公开(公告)日：2014-11-06

申请号：US13875810

申请日：2013-05-02

Applicant: ARM Limited

Inventor： Anders Lassen ,  Jorn Nystad

IPC: G06T1/60

CPC classification number: G06T1/60 ,  G06T11/001 ,  G06T11/40 ,  G06T15/005 ,  G09G5/39 ,  G09G2360/122

Abstract: A tile-based graphics processing pipeline comprising a rasteriser 3, a renderer 6, a tile buffer 10 configured to store rendered fragment data locally to the graphics processing pipeline prior to that data being written out to an external memory, a write out stage 13 configured to write data stored in the tile buffer to an external memory, and a programmable processing stage 14. The programmable processing stage 14 is operable under the control of graphics program instructions to read fragment data stored in the tile buffer 10 on a random access basis, perform a processing operation using the read fragment data, and write the result of the processing operation into the tile buffer 10 or to an external memory.

Abstract translation: 基于瓦片的图形处理流水线，包括光栅化器3，渲染器6，瓦片缓冲器10，其被配置为在将数据写入外部存储器之前将绘制的片段数据本地存储到图形处理流水线;配置 将存储在瓦片缓冲器中的数据写入外部存储器和可编程处理级14.可编程处理级14可在图形程序指令的控制下操作，以随机存取的方式读取存储在瓦片缓冲器10中的片段数据， 使用读取的片段数据执行处理操作，并将处理操作的结果写入片缓冲器10或外部存储器。

公开(公告)号：US20140327671A1

公开(公告)日：2014-11-06

申请号：US13875822

申请日：2013-05-02

Applicant: ARM Limited

Inventor： Jorn Nystad ,  Andreas Engh-Halstvedt ,  Sandeep Kakarlapudi ,  Michael Stokes

IPC: G06T15/00 ,  G06T15/80

CPC classification number: G06T15/005

Abstract: A tile-based graphics processing pipeline 1 comprising a rasteriser 3, a renderer 6, a tile buffer 10, a write out stage 13 and a programmable processing stage 14. The tile buffer 10 stores multiple render targets for a deferred shading operation and the programmable processing stage 14 is operable to, under the control of graphics program instructions, read data from two or more of a set of multiple render targets for a deferred shading operation stored in the tile buffer 10, perform a deferred shading processing operation using the read data, and to write the result of the processing operation to an output render target in the tile buffer 10, or to external memory.

Abstract translation: 包括光栅化器3，渲染器6，瓦片缓冲器10，写入级13和可编程处理级14的基于瓦片的图形处理流水线1.瓦片缓冲器10存储用于延迟着色操作和可编程 处理阶段14可操作以在图形程序指令的控制下从存储在瓦片缓冲器10中的延迟着色操作的一组多个渲染目标中的两个或更多个读取数据，使用读取的数据执行延迟着色处理操作 并将处理操作的结果写入瓦片缓冲器10中的输出渲染目标，或写入外部存储器。

公开(公告)号：US20140152683A1

公开(公告)日：2014-06-05

申请号：US13690151

申请日：2012-11-30

Applicant: ARM LIMITED

Inventor： Jorn Nystad ,  Andreas Engh-Halstvedt ,  Edvard Sorgard ,  Thomas Jeremy Olson ,  Marius Bjorge

IPC: G06T11/00

CPC classification number: G06T15/04 ,  G06T1/60

Abstract: A graphics virtual texturing system in which textures stored in a storage medium of a host system are divided into respective pages that are then loaded into a local memory of a graphics processing system for use. If the texture page that is required for performing a texturing operation at an originally desired level of detail (52) is not present in the local memory of the graphics processing system (53), the virtual texture lookup process loops back to try to sample the texture at an increased level of detail (55), and so on, until texture data that can be used is found in the local memory of the graphics processing system (53). This allows the texturing operation to proceed using texture data for the texel positions in question from a higher level (less detailed) mipmap in place of the originally desired texture data.

Abstract translation: 图形虚拟纹理系统，其中存储在主机系统的存储介质中的纹理被划分为相应的页面，然后将其加载到图形处理系统的本地存储器中以供使用。 如果在图形处理系统（53）的本地存储器中不存在用于以最初期望的细节级（52）执行纹理化操作所需的纹理页面，则虚拟纹理查找过程循环回来以尝试对 纹理处于增加的细节水平（55），等等，直到在图形处理系统（53）的本地存储器中找到可以使用的纹理数据。 这允许纹理化操作从较高级别（较不详细的）mipmap继续使用所讨论的纹素位置的纹理数据来代替原始期望的纹理数据。

公开(公告)号：US20130141445A1

公开(公告)日：2013-06-06

申请号：US13690142

申请日：2012-11-30

Applicant: ARM Limited

Inventor： Andreas Engh-halstvedt ,  Jorn Nystad ,  Frode Heggelund ,  Ronny Pedersen

IPC: G06T5/00

CPC classification number: G06T5/002 ,  G06T11/40 ,  G06T15/503 ,  G06T2200/28

Abstract: When carrying out a second, higher level of anti-aliasing such as 8× MSAA, in a graphics processing pipeline 1 configured to “natively” support a first level of anti-aliasing, such as 4× MSAA, the rasterisation stage 3, early Z (depth) and stencil test stage 4, late Z (depth) and stencil test stage 7, blending stage 9, and downsampling and writeback (multisample resolve) stage 11 of the graphics processing pipeline 1 process each graphics fragment or pixel that they receive for processing in plural processing passes, each such processing pass processing a sub-set of the sampling points that the fragment represents, but the fragment shader 6 is configured to process each graphics fragment in a processing pass that processes all the sampling points that the fragment represents in parallel, so as to ensure compliance with the desired higher level of multisampled anti-aliasing.

Abstract translation: 在图形处理流水线1中执行第二次更高水平的抗锯齿（例如8×MSAA），该图形处理管线1被配置为“本地地”支持第一水平的抗锯齿，例如4×MSAA，光栅化阶段3，早 Z（深度）和模板测试阶段4，后期Z（深度）和模板测试阶段7，混合阶段9和图形处理流水线1的下采样和回写（多采样分辨）阶段11处理它们接收的每个图形片段或像素 为了在多个处理通道中进行处理，每个这样的处理通过处理片段表示的采样点的子集，但是片段着色器6被配置为在处理所有采样点的处理通过中处理每个图形片段，片段 并行表示，以确保符合所需的更高级别的多采样抗锯齿。

公开(公告)号：US10825125B2

公开(公告)日：2020-11-03

申请号：US16139408

申请日：2018-09-24

Applicant: Arm Limited

Inventor： Jorn Nystad ,  Carmelo Giliberto ,  Edvard Fielding

IPC: G06T11/00 ,  G06T15/00 ,  G06T1/20 ,  G06T1/60 ,  G06T15/04

Abstract: A texture mapping apparatus, e.g. of a graphics processing unit, comprises texture fetching circuitry operable to receive a set of weight values for a convolution operation and fetch from memory a set of input data values on which the convolution operation is to be performed. The texture mapping apparatus further comprises texture filtering circuitry operable to perform a convolution operation using the set of received weight values and the set of fetched input data values. The texture mapping apparatus can allow a graphics processing unit to perform a variety of convolution operations in an efficient manner.

公开(公告)号：US10559055B2

公开(公告)日：2020-02-11

申请号：US15218016

申请日：2016-07-23

Applicant: ARM Limited

Inventor： Jorn Nystad

IPC: G06T1/20 ,  G06T15/00

Abstract: A programmable execution unit of a graphics processor that executes program instructions to perform graphics shading operations can use at least two different register file mapping configurations for mapping registers to execution threads.When a shader program is to be executed, how the shader program will use the registers is considered and the register file mapping configuration to use for the shader program is then selected based on the assessment of the register use by the shader program.Appropriate state information is then set to cause the threads being executed by the programmable execution unit to use the registers according to the selected register file mapping configuration when executing the shader program.

公开(公告)号：US10204391B2

公开(公告)日：2019-02-12

申请号：US13909556

申请日：2013-06-04

Applicant: ARM Limited

Inventor： Frode Heggelund ,  Jorn Nystad

IPC: G06T1/20

Abstract: A tile-based graphics processing pipeline that uses primitive lists that can encompass plural rendering tiles includes a primitive list reading unit that reads primitive lists for a tile being rendered to determine primitives to be processed for the tile and a rasterizer that rasterizes input primitives to generate graphics fragments to be processed. The pipeline further comprises a comparison unit between the primitive list reading unit and the rasterizer that for primitives that have been read from primitive lists that include plural rendering tiles, compares the location of the primitive in the render target to the location of the tile being rendered, and then either sends the primitive onwards to the rasterizer if the comparison determines that the primitive could lie at least partially within the tile, or does not send the primitive to the rasterizer if the comparison determines that the primitive definitely does not lie within the tile.

公开(公告)号：US20180108167A1

公开(公告)日：2018-04-19

申请号：US15564722

申请日：2016-04-06

Applicant: Arm Limited

Inventor： Jorn Nystad

IPC: G06T15/00

Abstract: A graphics processing pipeline (30) includes a programmable fragment shader (40) that is operable to, in response to a “test” instruction included in a fragment shader program that it is executing, trigger, if appropriate, the performance of an alpha-to-coverage operation (41), a late stencil test (42), and a late depth test (43) for a fragment being processed, and to then return updated coverage information to the fragment shader (40). This allows alpha-to-coverage and late stencil and depth test operations to be triggered and performed during shader execution, rather than having to wait until shader execution has been completed before performing those operations.