公开(公告)号：US20160357554A1

公开(公告)日：2016-12-08

申请号：US14731789

申请日：2015-06-05

Applicant: ARM LIMITED

Inventor： Ian Michael CAULFIELD ,  Peter Richard GREENHALGH ,  Simon John CRASKE ,  Max John BATLEY ,  Allan John SKILLMAN ,  Antony John PENTON

IPC: G06F9/30

CPC classification number: G06F9/3836 ,  G06F9/3855 ,  G06F9/3873 ,  G06F9/3889

Abstract: An apparatus comprises a processing pipeline comprising out-of-order execution circuitry and second execution circuitry. Control circuitry monitors at least one reordering metric indicative of an extent to which instructions are executed out of order by the out-of-order execution circuitry, and controls whether instructions are executed using the out-of-order execution circuitry or the second execution circuitry based on the reordering metric. A speculation metric indicative of a fraction of executed instructions that are flushed due to a mis-speculation can also be used to determine whether to execute instructions on first or second execution circuitry having different performance or energy consumption characteristics.

Abstract translation: 一种装置包括一个包括无序执行电路和第二执行电路的处理流水线。 控制电路监视至少一个重新排序度量，其指示由无序执行电路执行的指令不顺序的程度，并且控制是否使用无序执行电路或第二执行电路来执行指令 基于重新排序指标。 指示由于错误推测而被刷新的执行指令的一部分的猜测度量也可以用于确定是否执行具有不同性能或能量消耗特性的第一或第二执行电路上的指令。

公开(公告)号：US20160292021A1

公开(公告)日：2016-10-06

申请号：US15066453

申请日：2016-03-10

Applicant: ARM LIMITED

Inventor： Michael John WILLIAMS ,  Simon John CRASKE

IPC: G06F9/54 ,  G06F9/52

CPC classification number: G06F9/542

Abstract: In an apparatus performing multi-threaded data processing event handling circuitry receives event information from the data processing circuitry indicative of an event which has occurred during the data processing operations. Visibility configuration storage holds a set of visibility configuration values, each visibility configuration value associated with a thread of the multiple threads and the event handling circuitry adapts its use of the event information to restrict visibility of the event information for software of threads other than the thread which generated the event information when a visibility configuration value for the thread which generated the event information has a predetermined value. This allows multi-threaded event monitoring to be supported, whilst protecting event information from a particular thread for which it is desired to limit its visibility to software of other threads.

Abstract translation: 在执行多线程数据处理的装置中，事件处理电路从表示在数据处理操作期间发生的事件的数据处理电路接收事件信息。 可见性配置存储保存一组可见性配置值，与多个线程的线程相关联的每个可见性配置值和事件处理电路适应其对事件信息的使用，以限制线程以外的线程的事件信息的可见性 当生成事件信息的线程的可见性配置值具有预定值时，生成事件信息。 这允许支持多线程事件监视，同时保护来自希望限制其对其他线程的软件的可见性的特定线程的事件信息。

公开(公告)号：US20160063242A1

公开(公告)日：2016-03-03

申请号：US14935504

申请日：2015-11-09

Applicant: ARM Limited

Inventor： Thomas Christopher GROCUTT ,  Richard Roy GRISENTHWAITE ,  Simon John CRASKE

IPC: G06F21/52

CPC classification number: G06F21/52 ,  G06F9/30134 ,  G06F9/462 ,  G06F2221/034 ,  G06F2221/2105

Abstract: A data processing apparatus includes processing circuitry and a data store including a plurality of regions including a secure region and a less secure region. The secure region is configured to store sensitive data accessible by the circuitry when operating in a secure domain and not accessible by the circuitry when operating in a less secure domain. The data store includes a plurality of stacks with a secure stack in the secure region. Stack access circuitry is configured to store predetermined processing state to the secure stack. The processing circuitry further comprises fault checking circuitry configured to identify a first fault condition if the data stored in the predetermined relative location is the first value. This provides protection against attacks from the less secure domain, for example performing a function call return from an exception, or an exception return from a function call.

公开(公告)号：US20160048423A1

公开(公告)日：2016-02-18

申请号：US14793914

申请日：2015-07-08

Applicant: ARM LIMITED

Inventor： Michael WILLIAMS ,  Simon John CRASKE ,  Loïc PIERRON

IPC: G06F11/10 ,  H04L1/00

CPC classification number: G06F11/1004 ,  H04L1/004 ,  H04L1/0045 ,  H04L1/0061 ,  H04L2001/0094

Abstract: Transmission control checking circuitry adds control check data to a transaction response which is received at a transaction master and compared with expected data at the transaction master. The expected data having control check data may be a unique transaction identifier. The transaction master generated the unique transaction identifier when it generated the transaction request and will check that the transaction responses include that unique transaction identifier. In this way, errors in the control of transmission of transactions (e.g., misrouting) may be detected.

Abstract translation: 传输控制检查电路将控制检查数据添加到事务响应中，该事务响应在事务主机处接收并与交易主机处的预期数据进行比较。 具有控制检查数据的预期数据可以是唯一的事务标识符。 交易主机在生成事务请求时生成唯一的事务标识符，并检查事务响应是否包含该唯一事务标识符。 以这种方式，可以检测到事务传输控制中的错误（例如错误路由）。

公开(公告)号：US20150371017A1

公开(公告)日：2015-12-24

申请号：US14310332

申请日：2014-06-20

Applicant: ARM Limited

Inventor： Simon John CRASKE ,  Thomas Christopher Grocutt

IPC: G06F21/30

CPC classification number: G06F21/79 ,  G06F9/3806 ,  G06F21/554 ,  G06F2221/2141 ,  G06F2221/2149

Abstract: A data processing apparatus 2 supports operation in both a secure domain and a less secure domain. The secure domain has access to data that is not accessible when operating the less secure domain. Prediction circuitry 42 generates a domain prediction indicating whether a given processing action (such as a memory access) is to be performed in association with the secure domain or with the less secure domain. In this way, an appropriate set of memory permission data 34, 36 for controlling access by different privilege levels in the domains may be selected and applied by an appropriate memory protection unit. If the domain prediction is incorrect, then the processing is stalled and the given processing action retried.

Abstract translation: 数据处理装置2支持安全域和较不安全域的操作。 安全域可以访问在操作较不安全的域时无法访问的数据。 预测电路42产生指示是否要与安全域相关联地执行给定处理动作（诸如存储器访问）的域预测或者较不安全的域。 以这种方式，可以由适当的存储器保护单元选择适当的用于控制域中不同特权级别的访问的存储器许可数据34,36。 如果域预测不正确，则停止处理并重试给定的处理动作。

公开(公告)号：US20150220465A1

公开(公告)日：2015-08-06

申请号：US14581290

申请日：2014-12-23

Applicant: ARM Limited

Inventor： Michael KENNEDY ,  Simon John CRASKE ,  Andrew TURNER ,  Richard Anthony LANE

IPC: G06F13/26

CPC classification number: G06F13/1684

Abstract: A data processing system 2 includes an interrupt controller having a priority level arbitrator 10 and trigger circuitry 12. The priority level arbitrator 10 and the trigger circuitry 12 operate in parallel to process interrupt signals received by an interrupt signal receiver 6. The trigger circuitry 12 generates a trigger signal initiating interrupt processing before the priority level arbitrator 10 has completed its arbitration determination at an arbitration-completed time. If the interrupt processing triggered by the trigger signal was inappropriate, then is terminated once the result of the arbitration is known after the arbitration-completed time.

Abstract translation: 数据处理系统2包括具有优先级仲裁器10和触发电路12的中断控制器。优先权级别仲裁器10和触发电路12并行地操作以处理由中断信号接收器6接收的中断信号。触发电路12产生 在优先级仲裁器10在仲裁完成时间完成其仲裁确定之前，触发信号启动中断处理。 如果由触发信号触发的中断处理不合适，则在仲裁完成时间之后仲裁结果被知道后终止。

公开(公告)号：US20130339686A1

公开(公告)日：2013-12-19

申请号：US13968991

申请日：2013-08-16

Applicant: ARM Limited

Inventor： John Michael HORLEY ,  Simon John CRASKE ,  Michael John GIBBS ,  Paul Anthony GILKERSON

IPC: G06F9/30

CPC classification number: G06F11/3495 ,  G06F9/30072 ,  G06F9/30094 ,  G06F9/30101 ,  G06F9/30123 ,  G06F9/30145 ,  G06F11/348

Abstract: A processing circuit is responsive to at least one conditional instruction to perform a conditional operation in dependence on a current value of a subset of at least one condition flag. A trace circuit is provided for generating trace data elements indicative of operations performed by the processing circuit. When the processing circuit 4 processes at least one selected instruction, then the trace circuit generates a trace data element including a traced condition value indicating at least the subset of condition flags required to determine the outcome of the conditional instruction. A corresponding diagnostic apparatus uses the traced condition value to determine a processing outcome of the at least one conditional instruction.

Abstract translation: 处理电路响应于至少一个条件指令，以根据至少一个条件标志的子集的当前值执行条件操作。 提供跟踪电路用于产生指示由处理电路执行的操作的跟踪数据元素。 当处理电路4处理至少一个所选择的指令时，跟踪电路产生跟踪数据元素，跟踪数据元素包括至少指示确定条件指令的结果所需的条件标志的子集的跟踪条件值。 相应的诊断装置使用跟踪条件值来确定至少一个条件指令的处理结果。

公开(公告)号：US20220100673A1

公开(公告)日：2022-03-31

申请号：US17310368

申请日：2020-01-29

Applicant: ARM LIMITED

Inventor： Simon John CRASKE ,  Jacob EAPEN

IPC: G06F12/10 ,  G06F12/14

Abstract: There is provided an apparatus comprising input circuitry that receives requests comprising input addresses in an input domain. Output circuitry provides output addresses. The output addresses comprise secure physical addresses to secure storage circuitry and non-secure physical addresses to non-secure storage circuitry. Lookup circuitry stores a plurality of mappings comprising at least one mapping between the input addresses and the secure physical addresses, and at least one mapping between the input addresses and the non-secure physical addresses.

公开(公告)号：US20210208968A1

公开(公告)日：2021-07-08

申请号：US16732465

申请日：2020-01-02

Applicant: Arm Limited

Inventor： Mark Gerald LAVINE ,  Simon John CRASKE

IPC: G06F11/10 ,  G11C29/36

Abstract: A data processing apparatus is provided, which includes storage circuitry comprising a plurality of lines, each of the plurality of lines comprising a data value. Access circuitry accesses a pair of the plurality of lines at a time, the pair of the plurality of lines comprising a further data value, distinct from the data value, and a plurality of error bits to detect or correct errors in the data value in each line in the pair of the plurality of lines.

公开(公告)号：US20210097005A1

公开(公告)日：2021-04-01

申请号：US16583539

申请日：2019-09-26

Applicant: Arm Limited

Inventor： Simon John CRASKE

IPC: G06F12/14 ,  G06F12/02

Abstract: An apparatus and method are provided for performing data processing operations. The apparatus has processing circuitry for performing data processing operations configured to operate in a normal mode and a memory region management mode. A memory is used to store data accessed by the processing circuitry when performing the data processing operations. A memory region table is provided to define accessibility control information for each of a number of memory regions within the memory. An access control mechanism controls access to the memory in response to an access request issued by the processing circuitry, and a memory protection unit providing a bypass indication for one or more memory regions is referenced by the access control mechanism when the processing circuitry is in the memory region management mode. The access control mechanism is arranged to constrain access to the memory location identified by the access request based on the accessibility control information defined in the memory region management mode when the processing circuitry is operating in the normal mode. When the processing circuitry is operating in the memory region management mode, the access control mechanism is arranged to reference the memory protection unit and when the bypass indication is set for the memory region, to process the access to the memory location unconstrained by the memory region table.