公开(公告)号：US11269649B2

公开(公告)日：2022-03-08

申请号：US16078780

申请日：2017-03-17

Applicant: ARM LIMITED

Inventor： Thomas Christopher Grocutt

IPC: G06F9/30 ,  G06F9/38 ,  G06F9/34

Abstract: Processing circuitry performs multiple beats of processing in response to a vector instruction, each beat comprising processing corresponding to a portion of a vector value comprising multiple data elements. The processing circuitry sets beat status information indicating which beats of a group of two or more vector instructions have completed. In response to a return-from-event request indicating a return to processing of a given vector instruction, the processing circuitry resumes processing of the group of uncompleted vector instructions while suppressing beats already completed, based on the beat status information.

公开(公告)号：US10963251B2

公开(公告)日：2021-03-30

申请号：US16314882

申请日：2017-06-15

Applicant: ARM LIMITED

Inventor： Thomas Christopher Grocutt

IPC: G06F9/312 ,  G06F9/345 ,  G06F15/80 ,  G06F17/16 ,  G06F9/30

Abstract: There is provided an apparatus that includes a set of vector registers, each of the vector registers being arranged to store a vector comprising a plurality of portions. The set of vector registers is logically divided into a plurality of columns, each of the columns being arranged to store a same portion of each vector. The apparatus also includes register access circuitry that comprises a plurality of access blocks. Each access block is arranged to access a portion in a different column when accessing one of the vector registers than when accessing at least one other of the vector registers. The register access circuitry is arranged to simultaneously access portions in any one of: the vector registers and the columns.

公开(公告)号：US10831494B2

公开(公告)日：2020-11-10

申请号：US15774066

申请日：2016-10-18

Applicant: ARM LIMITED ,  THE CHANCELLOR, MASTERS AND SCHOLARS OF THE UNIVERSITY OF CAMBRIDGE

Inventor： Thomas Christopher Grocutt ,  Sam Ainsworth ,  Timothy Martin Jones

IPC: G06F9/30 ,  G06F9/38 ,  G06F12/0862 ,  G06F12/0875 ,  G06F12/1027

Abstract: A main processor 4 executes a main program and has an associated cache memory 6. Event detection circuitry 12 detects events consequent upon execution of the main program and indicative of data to be used by the main processor. One or more programmable further processors 16, 18 is triggered to execute a further program by the events detected by the event detection circuitry 12. Prefetch circuitry 28 is responsive to the further program executed by the one or more programmable further processors to trigger prefetching of the data to be used by the main processor to the cache memory.

公开(公告)号：US10303399B2

公开(公告)日：2019-05-28

申请号：US15834434

申请日：2017-12-07

Applicant: ARM LIMITED

Inventor： François Christopher Jacques Botman ,  Thomas Christopher Grocutt

IPC: G06F9/30 ,  G06F3/06 ,  G06F9/345

Abstract: An apparatus and method are provided for controlling vector memory accesses. The apparatus comprises a set of vector registers, and flag setting circuitry that is 5 responsive to a determination that a vector generated for storage in one of the vector registers comprises a plurality of elements that meet specified contiguousness criteria, to generate flag information associated with that vector register. Processing circuitry is then used to perform a vector memory access operation in order to access in memory a plurality of data values at addresses determined from an address vector operand 10 comprising a plurality of address elements. The address vector operand is provided in a specified vector register of the vector register set, such that the plurality of elements of the vector stored in that specified vector register form the plurality of address elements. The processing circuitry is arranged to determine whether the specified vector register has flag information associated therewith, and if it does, then that flag information is 15 used when determining a number of accesses to memory required to access the plurality of data values. This provides an efficient mechanism for allowing gather or scatter type memory access operations to be implemented using a reduced number of accesses to memory in certain situations where the flag information has been generated for the associated address vector operand.

公开(公告)号：US10073777B2

公开(公告)日：2018-09-11

申请号：US14579405

申请日：2014-12-22

Applicant: ARM Limited

Inventor： Thomas Christopher Grocutt

IPC: G06F12/0813 ,  G06F12/06 ,  G06F12/14

CPC classification number: G06F12/0813 ,  G06F12/06 ,  G06F12/1441 ,  Y02D10/13

Abstract: A data processing apparatus has a memory attribute unit having storage regions for storing attribute data for controlling access to a corresponding memory address range by processing circuitry. In response to a target memory address, the processing circuitry can perform a region identifying operation to output a region identifying value identifying which of the storage regions of the attribute unit corresponds to the target memory address. The region identifying value is made available to at least some software executed by the data processing apparatus. This can be useful for quickly checking access permissions of a range of addresses or for determining how to update the memory attribute unit.

公开(公告)号：US20180210805A1

公开(公告)日：2018-07-26

申请号：US15838615

申请日：2017-12-12

Applicant: ARM Limited

Inventor： François Christopher Jacques Botman ,  Thomas Christopher Grocutt ,  John Michael Horley

IPC: G06F11/34 ,  G06F7/548 ,  G06F9/30

CPC classification number: G06F11/3466 ,  G06F7/548 ,  G06F9/3001 ,  G06F9/30018 ,  G06F9/30036 ,  G06F9/30043 ,  G06F11/141 ,  G06F11/3471 ,  G06F11/3476

Abstract: An apparatus and method are provided for generating and processing a trace stream indicative of execution of predicated vector memory access instructions by processing circuitry. An apparatus has an input interface to receive execution information from the processing circuitry indicative of operations performed by that processing circuitry when executing a sequence of instructions. The sequence includes at least one predicated vector memory access instruction executed to perform a memory transfer operation in order to transfer data values of a vector between a vector register and addresses accessed in memory. The vector comprises a plurality of lanes, where the number of lanes is dependent on the size of the data values represented within the vector, and predicate information referenced when executing the predicated vector memory access instruction is used to determine which lanes are subjected to the memory transfer operation. The apparatus has trace generation circuitry to generate from the execution information a data trace stream comprising a plurality of trace elements. For each predicated vector memory access instruction executed, the trace generation circuitry is arranged to issue within the data trace stream a number of address trace elements, each address trace element providing an address indication for an address accessed in memory, and each address trace element being associated with a fixed sized data block irrespective of the size of the data values accessed when executing the memory access instruction. The trace generation circuitry further issues within the data trace stream, for each predicated vector memory access instruction executed, at least one predicate trace element to identify any lanes of the vector that have been omitted from the memory transfer operation. It has been found that such an approach provides a particularly bandwidth efficient mechanism for tracing predicated vector memory access instructions.

公开(公告)号：US20150371017A1

公开(公告)日：2015-12-24

申请号：US14310332

申请日：2014-06-20

Applicant: ARM Limited

Inventor： Simon John CRASKE ,  Thomas Christopher Grocutt

IPC: G06F21/30

CPC classification number: G06F21/79 ,  G06F9/3806 ,  G06F21/554 ,  G06F2221/2141 ,  G06F2221/2149

Abstract: A data processing apparatus 2 supports operation in both a secure domain and a less secure domain. The secure domain has access to data that is not accessible when operating the less secure domain. Prediction circuitry 42 generates a domain prediction indicating whether a given processing action (such as a memory access) is to be performed in association with the secure domain or with the less secure domain. In this way, an appropriate set of memory permission data 34, 36 for controlling access by different privilege levels in the domains may be selected and applied by an appropriate memory protection unit. If the domain prediction is incorrect, then the processing is stalled and the given processing action retried.

Abstract translation: 数据处理装置2支持安全域和较不安全域的操作。 安全域可以访问在操作较不安全的域时无法访问的数据。 预测电路42产生指示是否要与安全域相关联地执行给定处理动作（诸如存储器访问）的域预测或者较不安全的域。 以这种方式，可以由适当的存储器保护单元选择适当的用于控制域中不同特权级别的访问的存储器许可数据34,36。 如果域预测不正确，则停止处理并重试给定的处理动作。

公开(公告)号：US09202071B2

公开(公告)日：2015-12-01

申请号：US13741709

申请日：2013-01-15

Applicant: ARM Limited

Inventor： Thomas Christopher Grocutt ,  Richard Roy Grisenthwaite

IPC: G06F21/00 ,  G06F21/60 ,  G06F21/52 ,  G06F21/74 ,  G06F9/30

CPC classification number: G06F21/606 ,  G06F9/3009 ,  G06F9/30101 ,  G06F21/52 ,  G06F21/74 ,  G06F2209/481 ,  G06F2221/2105

Abstract: A data processing apparatus and method are provided for handling exceptions, including processing circuitry configured to perform data processing operations in response to program code, said circuitry including exception control circuitry. A plurality of registers are provided including a first and second subsets of registers, and a data store. The data store includes a secure region and a less secure region, wherein the secure region is for storing data accessible by the processing circuitry when operating in a secure domain and not accessible by the processing circuitry when operating in a less secure domain. The exception control circuitry performs state saving of data from the first subset of registers before triggering the processing circuitry to perform an exception handling routine corresponding to the exception. Where background processing was performed by the processing circuitry in the secure domain, the exception control circuitry performs additional state saving of the data.

Abstract translation: 提供了一种用于处理异常的数据处理装置和方法，包括配置为响应于程序代码执行数据处理操作的处理电路，所述电路包括异常控制电路。 提供了多个寄存器，包括第一和第二寄存器子集，以及数据存储器。 数据存储器包括安全区域和较不安全的区域，其中安全区域用于存储当在安全域中操作时由处理电路可访问的数据，并且当在较不安全的域中操作时由处理电路不可访问。 异常控制电路在触发处理电路之前对寄存器的第一子集进行数据的状态保存，以执行与异常相对应的异常处理程序。 在由安全域中的处理电路执行背景处理的情况下，异常控制电路执行数据的附加状态保存。

公开(公告)号：US12067400B2

公开(公告)日：2024-08-20

申请号：US17757197

申请日：2020-11-05

Applicant: Arm Limited

Inventor： Thomas Christopher Grocutt

IPC: G06F9/38 ,  G06F9/30

CPC classification number: G06F9/3861 ,  G06F9/30054 ,  G06F9/30189

Abstract: Processing circuitry has a handler mode and a thread mode. In response to an exception condition, a switch to handler mode is made. In response to an intermodal calling branch instruction specifying a branch target address when the processing circuitry is in the handler mode, an instruction decoder controls the processing circuitry to save a function return address to a function return address storage location; switch a current mode of the processing circuitry to the thread mode; and branch to an instruction identified by the branch target address. This can be useful for deprivileging of exceptions.

公开(公告)号：US12067263B2

公开(公告)日：2024-08-20

申请号：US17907205

申请日：2021-02-08

Applicant: ARM LIMITED

Inventor： Thomas Christopher Grocutt ,  Andrew Brookfield Swaine ,  Alexander Donald Charles Chadwick

IPC: G06F3/06 ,  G06F12/0891

CPC classification number: G06F3/0622 ,  G06F3/0629 ,  G06F3/0673 ,  G06F12/0891

Abstract: Apparatuses, methods and techniques for controlling memory access in a data processing system are disclosed. The operating data processing system comprises multiple subsystems, each comprising at least one processing element and at least one peripheral device. Memory transaction control circuitry receives memory transaction information of a memory transaction comprising a stream identifier indicative of the issuing peripheral device. A main control register indicates an address of a stream table having multiple entries each comprising an owning subsystem identifier. At least one subsystem control register corresponding to each subsystem of the multiple subsystems stores memory access checking configuration information. On receipt of the memory transaction information an entry of the stream table is selected in dependence on the stream identifier. At least one subsystem control register. corresponding to the subsystem identified by the owning subsystem identifier of the entry is selected.