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    REGION BASED SPLIT-DIRECTORY SCHEME TO ADAPT TO LARGE CACHE SIZES
    32.
    发明申请
    REGION BASED SPLIT-DIRECTORY SCHEME TO ADAPT TO LARGE CACHE SIZES 有权

    公开(公告)号：US20220237117A1

    公开(公告)日：2022-07-28

    申请号：US17721809

    申请日：2022-04-15

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Vydhyanathan Kalyanasundharam ,  Kevin M. Lepak ,  Amit P. Apte ,  Ganesh Balakrishnan

    IPC: G06F12/0817

    Abstract: Systems, apparatuses, and methods for maintaining region-based cache directories split between node and memory are disclosed. The system with multiple processing nodes includes cache directories split between the nodes and memory to help manage cache coherency among the nodes' cache subsystems. In order to reduce the number of entries in the cache directories, the cache directories track coherency on a region basis rather than on a cache line basis, wherein a region includes multiple cache lines. Each processing node includes a node-based cache directory to track regions which have at least one cache line cached in any cache subsystem in the node. The node-based cache directory includes a reference count field in each entry to track the aggregate number of cache lines that are cached per region. The memory-based cache directory includes entries for regions which have an entry stored in any node-based cache directory of the system.

    LIGHT-WEIGHT MEMORY EXPANSION IN A COHERENT MEMORY SYSTEM
    36.
    发明申请
    LIGHT-WEIGHT MEMORY EXPANSION IN A COHERENT MEMORY SYSTEM 审中-公开

    公开(公告)号：US20200226081A1

    公开(公告)日：2020-07-16

    申请号：US16249649

    申请日：2019-01-16

    Applicant: Advanced Micro Devices, Inc. ,  ATI Technologies ULC

    Inventor： Vydhyanathan Kalyanasundharam ,  Philip Ng ,  Alexander J. Branover ,  Kevin M. Lepak

    IPC: G06F13/16 ,  G06F9/48 ,  G06F9/50 ,  G06F9/38

    Abstract: Systems, methods, and port controller designs employ a light-weight memory protocol. A light-weight memory protocol controller is selectively coupled to a Cache Coherent Interconnect for Accelerators (CCIX) port. Over an on-chip interconnect fabric, the light-weight protocol controller receives memory access requests from a processor and, in response, transmits associated memory access requests to an external memory through the CCIX port using only a proper subset of CCIX protocol memory transactions types including non-cacheable transactions and non-snooping transactions. The light-weight memory protocol controller is selectively uncoupled from the CCIX port and a remote coherent slave controller is coupled in its place. The remote coherent slave controller receives memory access requests and, in response, transmits associated memory access requests to a memory module through the CCIX port using cacheable CCIX protocol memory transaction types.

    REGION BASED SPLIT-DIRECTORY SCHEME TO ADAPT TO LARGE CACHE SIZES
    37.
    发明申请
    REGION BASED SPLIT-DIRECTORY SCHEME TO ADAPT TO LARGE CACHE SIZES 审中-公开

    公开(公告)号：US20200073801A1

    公开(公告)日：2020-03-05

    申请号：US16119438

    申请日：2018-08-31

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Vydhyanathan Kalyanasundharam ,  Kevin M. Lepak ,  Amit P. Apte ,  Ganesh Balakrishnan

    IPC: G06F12/0817

    Abstract: Systems, apparatuses, and methods for maintaining region-based cache directories split between node and memory are disclosed. The system with multiple processing nodes includes cache directories split between the nodes and memory to help manage cache coherency among the nodes' cache subsystems. In order to reduce the number of entries in the cache directories, the cache directories track coherency on a region basis rather than on a cache line basis, wherein a region includes multiple cache lines. Each processing node includes a node-based cache directory to track regions which have at least one cache line cached in any cache subsystem in the node. The node-based cache directory includes a reference count field in each entry to track the aggregate number of cache lines that are cached per region. The memory-based cache directory includes entries for regions which have an entry stored in any node-based cache directory of the system.

    Tag accelerator for low latency DRAM cache
    38.
    发明授权
    Tag accelerator for low latency DRAM cache 有权

    公开(公告)号：US10545875B2

    公开(公告)日：2020-01-28

    申请号：US15855838

    申请日：2017-12-27

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Vydhyanathan Kalyanasundharam ,  Kevin M. Lepak ,  Ganesh Balakrishnan ,  Ravindra N. Bhargava

    IPC: G06F12/0897 ,  G06F12/121

    Abstract: Systems, apparatuses, and methods for implementing a tag accelerator cache are disclosed. A system includes at least a data cache and a control unit coupled to the data cache via a memory controller. The control unit includes a tag accelerator cache (TAC) for caching tag blocks fetched from the data cache. The data cache is organized such that multiple tags are retrieved in a single access. This allows hiding the tag latency penalty for future accesses to neighboring tags and improves cache bandwidth. When a tag block is fetched from the data cache, the tag block is cached in the TAC. Memory requests received by the control unit first lookup the TAC before being forwarded to the data cache. Due to the presence of spatial locality in applications, the TAC can filter out a large percentage of tag accesses to the data cache, resulting in latency and bandwidth savings.

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