公开(公告)号：US07136973B2

公开(公告)日：2006-11-14

申请号：US10772855

申请日：2004-02-04

Applicant: Alan Welsh Sinclair

Inventor： Alan Welsh Sinclair

IPC: G06F12/00

CPC classification number: G06F3/0685 ,  G06F1/3268 ,  G06F3/0613 ,  G06F3/0617 ,  G06F3/0634 ,  G06F3/068 ,  G06F12/0866 ,  G06F2212/2022 ,  Y02D10/154

Abstract: A dual media storage device is provided. Two separate non-volatile mass storage devices, one having a faster access time and a lower capacity than the other, are combined into a single system. A storage controller can direct the flow of data into one device or the other, depending upon various conditions, which might include one mass storage device being unavailable or for certain caching schemes.

Abstract translation: 提供双媒体存储设备。 两个独立的非易失性大容量存储设备，一个具有更快的访问时间和一个比另一个更低的容量，被组合成单个系统。 根据可能包括一个大容量存储设备不可用或某些高速缓存方案的各种条件，存储控制器可以将数据流引导到一个设备或另一个设备中。

公开(公告)号：US06813678B1

公开(公告)日：2004-11-02

申请号：US09600708

申请日：2000-09-06

Applicant: Alan Welsh Sinclair ,  Sergei Anatolovich Gorobets

Inventor： Alan Welsh Sinclair ,  Sergei Anatolovich Gorobets

IPC: G06F1208

CPC classification number: G11C29/76 ,  G06F3/0626 ,  G06F3/0652 ,  G06F3/0679

Abstract: A memory system (10) comprising a non-volatile memory (18) having memory locations (38), and a controller (16) for writing data structures to and reading data structures from the memory. The system (10) is architecturally configured so that the locations (38) can be written to individually but are erasable only in blocks. The controller (16) forms one or more erasable units (39) which are each subdivided into cells (50) each consisting of a group of locations (38). The controller (16) writes data structures to and reads structures from each cell (50) on a per cell basis. The system (10) may comprise a controller (16) embedded in a FLASH memory card. Alternatively, the controller (16) may be embedded in, or implemented in, a host system such as a Personal Computer (PC).

Abstract translation: 一种存储系统（10），包括具有存储器位置（38）的非易失性存储器（18），以及用于将数据结构写入并从存储器读取数据结构的控制器（16）。 系统（10）在架构上被配置为使得可以单独地写入位置（38），但是仅以块为单位可擦除。 控制器（16）形成一个或多个可擦除单元（39），每个可擦除单元（39）被细分为每个由一组位置（38）组成的单元（50）。 控制器（16）将数据结构写入每个单元（50）并从每个单元读取结构（50）。 系统（10）可以包括嵌入在闪存卡中的控制器（16）。 或者，控制器（16）可以嵌入或实现在诸如个人计算机（PC）的主机系统中。

公开(公告)号：US06725321B1

公开(公告)日：2004-04-20

申请号：US09786418

申请日：2001-03-01

Applicant: Alan Welsh Sinclair ,  Natalia Victorovna Ouspenskaia ,  Richard Michael Taylor ,  Sergey Anatolievich Gorobets

Inventor： Alan Welsh Sinclair ,  Natalia Victorovna Ouspenskaia ,  Richard Michael Taylor ,  Sergey Anatolievich Gorobets

IPC: G06F1200

CPC classification number: G06F12/0246 ,  G06F3/0619 ,  G06F3/064 ,  G06F3/0679 ,  G06F2212/7202

Abstract: A memory system (10) having a solid state memory (6) comprising non-volatile individually addressable memory sectors (1) arranged in erasable blocks, and a controller (8) for writing to reading from the sectors, and for sorting the blocks into “erased” and “not erased” blocks. The controller performs logical to physical address translation, and includes a Write Pointer (WP) for pointing to the physical sector address to which data is to be written from a host processor. A Sector Allocation Table (SAT) of logical adrresses with respective physical addresses is stored in the memory, and the controller updates the SAT less frequently than sectors are written to with data from the host processor. The memory may be in a single chip, or in a plurality of chips. A novel system for arranging data in the individual sectors (1) is also claimed.

Abstract translation: 一种具有固态存储器（6）的存储器系统（10），该固态存储器（6）包括布置在可擦除块中的非易失性单独可寻址存储器扇区（1），以及用于写入从扇区读取并将块分类为 “擦除”和“不擦除”块。 控制器执行逻辑到物理地址转换，并且包括用于指向要从主机处理器写入数据的物理扇区地址的写指针（WP）。 具有相应物理地址的逻辑地址的扇区分配表（SAT）被存储在存储器中，并且控制器比扇区被写入的频率比主处理器的数据更频繁地更新SAT。 存储器可以在单个芯片中，或者在多个芯片中。 还要求用于在各个扇区（1）中排列数据的新颖系统。

公开(公告)号：US6069827A

公开(公告)日：2000-05-30

申请号：US46518

申请日：1998-03-24

Applicant: Alan Welsh Sinclair

Inventor： Alan Welsh Sinclair

IPC: G11C16/02 ,  G06F3/06 ,  G06F3/08 ,  G06F12/00 ,  G06F12/02 ,  G11C16/04

CPC classification number: G06F12/0238 ,  G06F12/0246 ,  G06F3/0601 ,  G06F2003/0694 ,  Y02B60/1225

Abstract: A solid state memory for emulating a disk drive comprising: translation means for translating a logical sector address to a main memory address; a main memory composed of non-volatile memory cells erasable in blocks; characterized in that a first pointer is used to point to an unwritten location in main memory, and a second pointer is used to point to the next unerased erasable block in sequence to the erasable block containing the said unwritten memory location; control means being provided to ensure that there is always at least one erasable block in the erased condition between the first and second pointers.

Abstract translation: 一种用于模拟磁盘驱动器的固态存储器，包括：用于将逻辑扇区地址转换为主存储器地址的转换装置; 由可擦除块的非易失性存储单元组成的主存储器; 其特征在于，第一指针用于指向主存储器中的未写入位置，并且第二指针用于依次指向包含所述未写入存储器位置的可擦除块的下一个未故障可擦除块; 提供控制装置以确保在第一和第二指针之间的擦除状态中总是存在至少一个可擦除块。

公开(公告)号：US07383375B2

公开(公告)日：2008-06-03

申请号：US11016271

申请日：2004-12-16

Applicant: Alan Welsh Sinclair

Inventor： Alan Welsh Sinclair

IPC: G06F12/00

CPC classification number: G06F12/0246 ,  G06F2212/7203

Abstract: Data in data runs are stored in a non-volatile memory array in adaptive metablocks that are configured according to the locations of data boundaries. A serial flash buffer is used to store some data, while other data are directly stored in non-volatile memory. Data may be stored with alignment to data boundaries during updating of the data to improve efficiency of subsequent updates.

Abstract translation: 数据运行中的数据存储在根据数据边界位置配置的自适应元区块中的非易失性存储器阵列中。 串行闪存缓存用于存储一些数据，而其他数据则直接存储在非易失性存储器中。 在更新数据期间，可以将数据与数据边界对准存储，以提高后续更新的效率。

公开(公告)号：US07310699B2

公开(公告)日：2007-12-18

申请号：US11541013

申请日：2006-09-29

Applicant: Alan Welsh Sinclair

Inventor： Alan Welsh Sinclair

IPC: G06F12/00

CPC classification number: G06F3/0656 ,  G06F3/0613 ,  G06F3/0685

Abstract: A data storage device is provided. A disk device is combined with a non-volatile memory device to provide much shorter write access time and much higher data write speed than can be achieved with a disk device alone. Interleaving bursts of sector writes between the two storage devices can effectively eliminate the effect of the seek time of the disk device. Following a non-contiguous logical address transition from a host system, the storage controller can perform a look-ahead seek operation on the disk device, while writing current data to the non-volatile memory device. Such a system can exploit the inherently faster write access characteristics of a non-volatile memory device, eliminating the dead time normally caused by the disk seek time.

Abstract translation: 提供数据存储装置。 磁盘设备与非易失性存储器件组合以提供比单独的磁盘设备可以实现的更短的写入访问时间和更高的数据写入速度。 在两个存储设备之间切换脉冲串扇区写入可以有效地消除磁盘设备的查找时间的影响。 在从主机系统进行不连续的逻辑地址转换之后，存储控制器可以在将当前数据写入非易失性存储器设备的同时对盘设备执行前瞻性查找操作。 这样的系统可以利用非易失性存储器件固有地更快的写入访问特性，从而消除通常由磁盘查找时间引起的死区时间。

公开(公告)号：US06578127B1

公开(公告)日：2003-06-10

申请号：US09164342

申请日：1998-10-01

Applicant: Alan Welsh Sinclair

Inventor： Alan Welsh Sinclair

IPC: G06F1208

CPC classification number: G06F3/0601 ,  G06F11/1435 ,  G06F12/0246 ,  G06F2003/0694

Abstract: A computer system has a memory device. The memory device includes a user interface, a controller, a store, and an address mapping device for mapping a first address from the user interface to a second address for accessing the store, where the controller stores information in successive regions of the store each time the information is updated.

Abstract translation: 计算机系统具有存储装置。 该存储装置包括一个用户界面，一个控制器，一个存储区和一个地址映射设备，用于将第一个地址从用户界面映射到用于访问存储的第二个地址，其中控制器每次在存储器的连续区域中存储信息 信息更新。

公开(公告)号：US06490649B2

公开(公告)日：2002-12-03

申请号：US10085914

申请日：2002-02-28

Applicant: Alan Welsh Sinclair

Inventor： Alan Welsh Sinclair

IPC: G06F1200

CPC classification number: G06F12/0246 ,  G06F2212/401

Abstract: An addressable memory device for storing blocks of varying length, utilizes a write pointer (18) to indicate the address of the next location to which data are to be written and an erase pointer (16) to indicate the address of the next location from which data are to be erased. It has a sector header (20) appended to each group of data containing information (38) indicating the length of the corresponding sector of data, and the location stored by the write pointer (14), which is selected to ensure that there is always at least one erased block adjacent to the current write block.

Abstract translation: 一种用于存储不同长度的块的可寻址存储器件，利用写指针（18）来指示要写入数据的下一个位置的地址和擦除指针（16），以指示下一个位置的地址 数据将被删除。 它具有附加到每个包含指示相应的数据扇区的长度的信息（38）的数据组的区段标题（20）和由写指针（14）存储的位置，其被选择以确保总是 与当前写入块相邻的至少一个擦除块。

公开(公告)号：US06345367B1

公开(公告)日：2002-02-05

申请号：US09214726

申请日：1999-02-16

Applicant: Alan Welsh Sinclair

Inventor： Alan Welsh Sinclair

IPC: G06F1120

CPC classification number: G11C29/70 ,  G11C16/16

Abstract: A fault tolerant memory system includes an array of block-erasable storage elements (12). Each block (12) of storage locations is sub-divided into sub-groups (14) of storage elements. A control information store means holds defect information for each group in each block and an address counter holds the addresses of the groups in the particular erase block being erased. A testing circuit checks whether the defect information stored in the control information store for the particular group currently addressed by the address counter indicates that the particular group contains one or more defective storage locations. If it does it increments the address counter.

Abstract translation: 容错存储器系统包括块可擦除存储元件（12）的阵列。 存储单元的每个块（12）被细分为存储元件的子组（14）。 控制信息存储装置保存每个块中每个组的缺陷信息，并且地址计数器保存擦除特定擦除块中的组的地址。 测试电路检查存储在控制信息存储器中的针对由地址计数器当前寻址的特定组的缺陷信息是否指示特定组包含一个或多个有缺陷的存储位置。 如果它增加地址计数器。

公开(公告)号：US3993918A

公开(公告)日：1976-11-23

申请号：US532259

申请日：1974-12-12

Applicant: Alan Welsh Sinclair

Inventor： Alan Welsh Sinclair

IPC: G11C11/411 ,  G11C19/28 ,  H01L21/822 ,  H01L27/02 ,  H01L27/04 ,  H01L27/102 ,  H03K3/286 ,  H03K3/289 ,  H03K23/08

CPC classification number: G11C11/4113 ,  G11C19/28 ,  H01L27/0233 ,  H01L27/1025 ,  H03K3/286 ,  H03K3/289

Abstract: A master/slave bistable arrangement which operates on current levels rather than voltage levels and with a single input of clock pulses. There are different bias current levels which are advantageously supplied by multi-layer current injection structures in integrated form.

Abstract translation: 主/从双稳态布置，其工作电流电平而不是电压电平和单个时钟脉冲输入。 存在不同的偏置电流水平，其有利地以集成的形式由多层电流注入结构提供。