公开(公告)号：US06734051B2

公开(公告)日：2004-05-11

申请号：US10341750

申请日：2003-01-13

Applicant: Cem Basceri ,  Irina Vasilyeva ,  Ammar Derraa ,  Philip H. Campbell ,  Gurtej S. Sandhu

Inventor： Cem Basceri ,  Irina Vasilyeva ,  Ammar Derraa ,  Philip H. Campbell ,  Gurtej S. Sandhu

IPC: H01L2184

CPC classification number: C23C16/4407 ,  C23C16/14 ,  C23C16/42 ,  C23C16/4404

Abstract: A first cleaning is conducted on a plasma enhanced chemical vapor deposition chamber at room ambient pressure. After the first cleaning, elemental titanium comprising layers are chemical vapor deposited on a first plurality of substrates within the chamber using at least TiCl4. Thereafter, titanium silicide comprising layers are plasma enhanced chemical vapor deposited on a second plurality of substrates within the chamber using at least TiCl4 and a silane. Thereafter, a second cleaning is conducted on the chamber at ambient room pressure. In one implementation after the first cleaning, an elemental titanium comprising layer is chemical vapor deposited over internal surfaces of the chamber while no semiconductor substrate is received within the chamber. In another implementation, a titanium silicide comprising layer is chemical vapor deposited over internal surfaces of the chamber while no semiconductor substrate is received within the chamber.

Abstract translation: 在室内环境压力下，在等离子体增强化学气相沉积室上进行第一次清洗。 在第一次清洁之后，使用至少TiCl 4，在室内的第一组多个衬底上化学气相沉积包含层的元素钛。 此后，包含层的硅化钛是使用至少TiCl 4和硅烷沉积在室内的第二多个基板上的等离子体增强化学气相。 此后，在室内在室内进行第二清洗。 在第一次清洁之后的一个实施方案中，元素钛包含层在室的内表面上化学气相沉积，而在室内没有接收半导体衬底。 在另一个实施方案中，包含硅化钛的层在室的内表面上化学气相沉积，而在腔室内不接收半导体衬底。

公开(公告)号：US06589803B2

公开(公告)日：2003-07-08

申请号：US10114492

申请日：2002-04-02

Applicant: Ammar Derraa

Inventor： Ammar Derraa

IPC: H01L2100

CPC classification number: H01J9/025

Abstract: A method for fabricating a field emission structure is disclosed. A first dielectric layer and a second material layer are disposed over a substrate and at least one emitter tip thereon. Planarization of the second layer exposes regions of the first layer that cover the emitter tip, which regions may then be removed through the second layer. Substantially removal of the second layer reduces any conductive defects that protrude from a surface of the first layer. A third, dielectric layer and fourth, grid layer are then formed. Planarization of the fourth layer forms grid openings and exposes dielectric material of the third layer which overlies the emitter tip. Dielectric material of one or both underlying layers may then be removed to expose the outer surfaces of the emitter tip.

公开(公告)号：US06197607B1

公开(公告)日：2001-03-06

申请号：US09260708

申请日：1999-03-01

Applicant: Ammar Derraa

Inventor： Ammar Derraa

IPC: H01L2100

CPC classification number: H01J9/025

Abstract: A method of fabricating a field emission array to facilitate optimization of the size of grid openings. The method also minimizes the occurrence of electrical shorts between the cathode and anode grid of the field emission array. In the method of the present invention, a first layer of dielectric material is disposed over a substrate and emitter tips of the field emission array. A second layer is disposed over the first layer and subsequently planarized to expose regions of the first layer that are located above the emitter tips. Dielectric material of the first layer may be removed through openings of the second layer to expose a top portion of each of the emitter tips. The second layer is then substantially removed from the first layer. Planarization and removal of the second layer may reduce any conductive defects that extend through the first layer. A third layer, which comprises dielectric material, is disposed over the first layer. A fourth layer of grid material is disposed over the third layer, then planarized to expose dielectric material located over the emitter tips. The dielectric material exposed through the fourth layer is removes to define grid openings or apertures through the fourth layer. Dielectric material may also be removed through the grid openings to space the first and third layers apart from the emitter tips. Field emission arrays fabricated in accordance with the method of the present invention are also within the scope of the present invention.

Abstract translation: 一种制造场致发射阵列以便于优化栅极开口尺寸的方法。 该方法还使得场发射阵列的阴极和阳极栅极之间的电短路的发生最小化。 在本发明的方法中，介电材料的第一层设置在衬底上，并且发射阵列的发射极尖端。 第二层设置在第一层上并随后被平坦化以暴露位于发射极尖端上方的第一层的区域。 可以通过第二层的开口去除第一层的电介质材料，以露出每个发射极尖端的顶部。 然后基本上从第一层移除第二层。 平面化和去除第二层可以减少延伸穿过第一层的任何导电缺陷。 包括电介质材料的第三层设置在第一层上。 第四层栅格材料设置在第三层上，然后被平坦化以暴露位于发射极尖端上方的介电材料。 通过第四层曝光的电介质材料被去除以限定通过第四层的栅格开口或孔。 电介质材料也可以通过网格开口去除以使第一和第三层与发射极尖端分开。 根据本发明的方法制造的场发射阵列也在本发明的范围内。

公开(公告)号：US6133057A

公开(公告)日：2000-10-17

申请号：US472571

申请日：1999-12-27

Applicant: Ammar Derraa

Inventor： Ammar Derraa

IPC: H01J9/02 ,  H01L21/00

CPC classification number: H01J9/025

Abstract: A method of fabricating a field emission array that employs a single mask to define the emitter tips thereof and their corresponding resistors. A layer of conductive material is disposed over a substrate of the field emission array. A plurality of substantially mutually parallel conductive lines is defined from the layer of conductive material. At least one layer of semiconductive material or conductive material is disposed over the conductive lines and over the regions of the substrate exposed between adjacent conductive lines. A mask material is disposed over the layer of semiconductive material or conductive material, substantially above each of the conductive lines. Portions of the layer of semiconductive material or conductive material exposed through the mask material may be removed to expose substantially longitudinal center portions of the conductive lines. Other portions of the layer of semiconductive material or conductive material may remain over peripheral lateral edges of the conductive lines. The mask material may be removed and the layer of semiconductive material or conductive material planarized. A mask is disposed over the field emission array and portions of the layer of semiconductive material or conductive material removed therethrough to define emitter tips and their corresponding resistors. The substantially longitudinal center portion of each of the conductive lines may be removed to electrically isolate adjacent columns of pixels of the field emission array from each other. Field emission arrays fabricated by the method of the present invention are also within the scope of the present invention.

公开(公告)号：US07518302B2

公开(公告)日：2009-04-14

申请号：US10420138

申请日：2003-04-21

Applicant: Ammar Derraa

Inventor： Ammar Derraa

IPC: H01J63/04

CPC classification number: H01J9/025

Abstract: Each pixel of a field emission device includes a resistor with at least one emitter tip thereover and at least one substantially vertically oriented conductive element positioned adjacent the resistor. In a field emission array, a conductive element may contact each resistor of a line of pixels. A method for fabricating the field emission array includes forming a plurality of substantially parallel conductive lines, depositing at least one layer of semiconductive or conductive material over and laterally adjacent each conductive line, and forming a hard mask in recesses of the surface of the uppermost material layer. The underlying material layer or layers are patterned through the hard mask, exposing substantially longitudinal center portions of the conductive lines. The remaining semiconductive or conductive material is patterned to form the emitter tips and resistors. At least the substantially central longitudinal portions of the conductive traces are removed to form the conductive elements.

公开(公告)号：US20060172088A1

公开(公告)日：2006-08-03

申请号：US11394989

申请日：2006-03-30

Applicant: Cem Basceri ,  Irina Vasilyeva ,  Ammar Derraa ,  Philip Campbell ,  Gurtej Sandhu

Inventor： Cem Basceri ,  Irina Vasilyeva ,  Ammar Derraa ,  Philip Campbell ,  Gurtej Sandhu

IPC: C23C16/14

CPC classification number: H01L21/28518 ,  C23C16/42 ,  H01L21/28556

Abstract: Chemical vapor deposition methods of forming titanium silicide including layers on substrates are disclosed. TiCl4 and at least one silane are first fed to the chamber at or above a first volumetric ratio of TiCl4 to silane for a first period of time. The ratio is sufficiently high to avoid measurable deposition of titanium silicide on the substrate. Alternately, no measurable silane is fed to the chamber for a first period of time. Regardless, after the first period, TiCl4 and at least one silane are fed to the chamber at or below a second volumetric ratio of TiCl4 to silane for a second period of time. If at least one silane was fed during the first period of time, the second volumetric ratio is lower than the first volumetric ratio. Regardless, the second feeding is effective to plasma enhance chemical vapor deposit a titanium silicide including layer on the substrate.

公开(公告)号：US07052350B1

公开(公告)日：2006-05-30

申请号：US09383331

申请日：1999-08-26

Applicant: Ammar Derraa

Inventor： Ammar Derraa

IPC: H01J9/00

CPC classification number: H01J3/021 ,  H01J1/3044 ,  H01J9/185 ,  H01J29/481 ,  H01J31/127

Abstract: An FED and a method of manufacture are provided. The FED includes a cathode assembly containing an improved column line structure. The column line structure includes a conductive structure formed on a substrate. A resistive layer is formed on the conductive structure, and an insulator layer is formed partly over the resistive layer. The contact between the base of the emitter tips and the addressing column line is achieved through a lateral side that is not covered by the insulator layer. The insulator layer helps reduce the possibility of electrical shorting between the addressing column line and the row line structure of the cathode assembly. The insulator layer on top of the addressing column line will allow the use of a thinner subsequent dielectric layer. This thinner dielectric layer, which supports the grid, will provide a lower RC time constant and help achieve better video rate operation. The thinner dielectric layer also will result in smaller grid openings above the tips. This will provide for better beam spots, and, therefore, better image resolution. The thinner dielectric layer will require less applied voltage to extract electrons from the tips, resulting in lower power consumption for the FED.

Abstract translation: 提供FED和制造方法。 FED包括具有改进的柱线结构的阴极组件。 列线结构包括形成在基板上的导电结构。 在导电结构上形成电阻层，部分地在电阻层上形成绝缘体层。 通过未被绝缘体层覆盖的侧面来实现发射极尖端的基极与寻址列线之间的接触。 绝缘体层有助于减少寻址列线和阴极组件的行线结构之间的电短路的可能性。 在寻址列线顶部的绝缘体层将允许使用更薄的后续介电层。 支持电网的这种较薄的介质层将提供较低的RC时间常数，有助于实现更好的视频速率操作。 更薄的介电层也将导致尖端上方的较小的栅极开口。 这将提供更好的光束点，因此，更好的图像分辨率。 更薄的电介质层将需要更少的施加电压以从尖端提取电子，导致FED的较低功耗。

公开(公告)号：US07033642B2

公开(公告)日：2006-04-25

申请号：US10666025

申请日：2003-09-17

Applicant: Cem Basceri ,  Irina Vasilyeva ,  Ammar Derraa ,  Philip H. Campbell ,  Gurtej S. Sandhu

Inventor： Cem Basceri ,  Irina Vasilyeva ,  Ammar Derraa ,  Philip H. Campbell ,  Gurtej S. Sandhu

IPC: C23C16/14 ,  C23C16/24

CPC classification number: H01L21/28518 ,  C23C16/42 ,  H01L21/28556

Abstract: Chemical vapor deposition methods of forming titanium silicide including layers on substrates are disclosed. TiCl4 and at least one silane are first fed to the chamber at or above a first volumetric ratio of TiCl4 to silane for a first period of time. The ratio is sufficiently high to avoid measurable deposition of titanium silicide on the substrate. Alternately, no measurable silane is fed to the chamber for a first period of time. Regardless, after the first period, TiCl4 and at least one silane are fed to the chamber at or below a second volumetric ratio of TiCl4 to silane for a second period of time. If at least one silane was fed during the first period of time, the second volumetric ratio is lower than the first volumetric ratio. Regardless, the second feeding is effective to plasma enhance chemical vapor deposit a titanium silicide including layer on the substrate.

Abstract translation: 公开了在衬底上形成包括层的硅化钛的化学气相沉积方法。 TiCl 4 S和至少一种硅烷首先以等于或高于TiCl 4的第一体积比与硅烷一起进料到室中，持续第一段时间。 该比例足够高以避免钛硅化物在衬底上的可测量沉积。 或者，在第一时间段内没有可测量的硅烷进料到室中。 无论如何，在第一阶段之后，将TiCl 4 S和至少一种硅烷以等于或低于TiCl 4的第二体积比与硅烷一起进料到室中，持续第二阶段 时间。 如果在第一时间段内进料至少一种硅烷，则第二体积比率低于第一体积比。 无论如何，第二次进料对于等离子体有效地提高了化学气相沉积在基底上的包含硅的硅化钛。

公开(公告)号：US06908849B2

公开(公告)日：2005-06-21

申请号：US10931854

申请日：2004-09-01

Applicant: Ammar Derraa ,  Sujit Sharan ,  Paul Castrovillo

Inventor： Ammar Derraa ,  Sujit Sharan ,  Paul Castrovillo

IPC: H01L21/285 ,  H01L21/4763 ,  H01L21/768 ,  H01L29/45

CPC classification number: H01L21/76846 ,  H01L21/28518 ,  H01L21/28556 ,  H01L21/76843 ,  H01L21/76855 ,  H01L21/76868 ,  H01L21/76877 ,  H01L29/456

Abstract: A high aspect ratio contact structure formed over a junction region in a silicon substrate comprises a titanium interspersed with titanium silicide layer that is deposited in the contact opening and directly contacts an upper surface of the substrate. Silicon-doping of CVD titanium, from the addition of SiH4 during deposition, reduces consumption of substrate silicon during the subsequent silicidation reaction in which the titanium reacts with silicon to form a titanium silicide layer that provides low resistance electrical contacts between the junction region and the silicon substrate. The contact structure further comprises a titanium nitride contact fill that is deposited in the contact opening and fills substantially the entire contact opening.

Abstract translation: 形成在硅衬底的接合区域上的高纵横比接触结构包括散布有硅化钛层的钛，其沉积在接触开口中并直接接触衬底的上表面。 在沉积期间从SiH 4 Si的添加中CVD钛的掺杂减少了在随后的硅化反应期间底物硅的消耗，其中钛与硅反应形成提供低电阻的硅化钛层 接合区域和硅衬底之间的电接触。 接触结构还包括氮化钛接触填料，其沉积在接触开口中并基本上填充整个接触开口。

公开(公告)号：US06730355B2

公开(公告)日：2004-05-04

申请号：US10094579

申请日：2002-03-06

Applicant: Ammar Derraa ,  Cem Basceri ,  Irina Vasilyeva ,  Philip H. Campbell ,  Gurtej S. Sandhu

Inventor： Ammar Derraa ,  Cem Basceri ,  Irina Vasilyeva ,  Philip H. Campbell ,  Gurtej S. Sandhu

IPC: C23C1642

CPC classification number: C23C16/4408 ,  C23C16/42 ,  C23C16/4405

Abstract: A first substrate is provided within a chemical vapor deposition chamber. A reactive gas mixture comprising TiCl4 and a silane is provided within the chamber effective to first chemically vapor deposit a titanium silicide comprising layer on the first substrate. After the first deposit, the first substrate is removed from the chamber. After the first deposit, a first cleaning is conducted within the chamber with a chlorine comprising gas. After the first cleaning, a second cleaning is conducted within the chamber with a hydrogen comprising gas. After the second cleaning and after the removing, a titanium silicide comprising layer is chemically vapor deposited over a second substrate within the chamber using a reactive gas mixture comprising TiCl4 and a silane. Other implementations are disclosed.

Abstract translation: 第一基板设置在化学气相沉积室内。 在室内提供包含TiCl 4和硅烷的反应气体混合物，其有效地首先在第一衬底上化学气相沉积包含硅化钛的层。 在第一次沉积之后，将第一衬底从腔室中取出。 在第一次沉积之后，在室内用含氯气体进行第一次清洗。 在第一次清洁之后，在室内用含氢气体进行第二次清洗。 在第二次清洁之后并且在除去之后，使用包含TiCl 4和硅烷的反应性气体混合物，在室内的第二衬底上化学气相沉积包含硅化钛的层。 公开了其他实现。