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公开(公告)号:US12104243B2
公开(公告)日:2024-10-01
申请号:US17348849
申请日:2021-06-16
Applicant: Applied Materials, Inc.
Inventor: Annamalai Lakshmanan , Jacqueline S. Wrench , Feihu Wang , Yixiong Yang , Joung Joo Lee , Srinivas Gandikota , Sang-heum Kim , Zhebo Chen , Gang Shen
IPC: C23C14/02 , C23C14/06 , C23C14/16 , C23C14/58 , C23C16/02 , C23C16/06 , C23C16/42 , C23C16/455 , C23C16/52 , C23C16/56
CPC classification number: C23C16/0281 , C23C14/021 , C23C14/025 , C23C14/0682 , C23C14/16 , C23C14/5886 , C23C16/0227 , C23C16/06 , C23C16/42 , C23C16/45527 , C23C16/52 , C23C16/56
Abstract: Methods and apparatus for processing a substrate is provided herein. For example, a method for processing a substrate comprises depositing a silicide layer within a feature defined in a layer on a substrate, forming one of a metal liner layer or a metal seed layer atop the silicide layer within the feature via depositing at least one of molybdenum (Mo) or tungsten (W) using physical vapor deposition, and depositing Mo using at least one of chemical vapor deposition or atomic layer deposition atop the at least one of the metal liner layer or the metal seed layer, without vacuum break.
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公开(公告)号:US20240274437A1
公开(公告)日:2024-08-15
申请号:US18644475
申请日:2024-04-24
Applicant: ASM IP Holding B.V.
Inventor: Amir Kajbafvala , Joe Margetis , Xin Sun , David Kohen , Dieter Pierreux
IPC: H01L21/02 , C23C16/08 , C23C16/24 , C23C16/42 , C23C16/455 , C23C16/52 , C30B25/16 , C30B25/18 , C30B29/06 , C30B29/52 , H01L29/06 , H01L29/423 , H01L29/786
CPC classification number: H01L21/0262 , C23C16/08 , C23C16/24 , C23C16/42 , C23C16/45523 , C23C16/52 , C30B25/165 , C30B25/18 , C30B29/06 , C30B29/52 , H01L21/02507 , H01L21/02532 , H01L21/02576 , H01L21/02579 , H01L21/02603 , H01L29/0673 , H01L29/42392 , H01L29/78696
Abstract: Methods and systems for forming structures including one or more layers comprising silicon germanium and one or more layers comprising silicon are disclosed. Exemplary methods can include using a surfactant, using particular precursors, and/or using a transition step to improve an interface between adjacent layers comprising silicon germanium and comprising silicon.
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公开(公告)号:US20240200188A1
公开(公告)日:2024-06-20
申请号:US18590141
申请日:2024-02-28
Applicant: Applied Materials, Inc.
Inventor: Feng Q. Liu , Hua Chung , Schubert Chu , Mei Chang , Jeffrey W. Anthis , David Thompson
IPC: C23C16/42 , C23C16/14 , C23C16/455 , C23C16/507 , C23C16/513 , C23C16/52
CPC classification number: C23C16/42 , C23C16/14 , C23C16/45536 , C23C16/45542 , C23C16/507 , C23C16/513 , C23C16/52
Abstract: Processing methods for forming iridium-containing films at low temperatures are described. The methods comprise exposing a substrate to iridium hexafluoride and a reactant to form iridium metal or iridium silicide films. Methods for enhancing selectivity and tuning the silicon content of some films are also described.
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公开(公告)号:US11942365B2
公开(公告)日:2024-03-26
申请号:US15994848
申请日:2018-05-31
Applicant: EUGENUS, INC.
Inventor: Vinayak Veer Vats , M. Ziaul Karim , Bo Seon Choi , Somilkumar J. Rathi , Niloy Mukherjee
IPC: C23C16/42 , C23C16/34 , C23C16/455 , C23C28/00 , H01L21/02 , H01L21/285 , H01L21/768 , H01L23/532
CPC classification number: H01L21/7685 , C23C16/34 , C23C16/345 , C23C16/42 , C23C16/45527 , C23C16/45529 , C23C28/00 , C23C28/321 , C23C28/34 , C23C28/345 , C23C28/36 , H01L21/02068 , H01L21/28518 , H01L21/28562 , H01L21/76841 , H01L23/53266 , H01L21/76846
Abstract: The disclosed technology generally relates to semiconductor structures and their fabrication, and more particularly to diffusion barrier structures containing Ti, Si, N and methods of forming same. A method of forming an electrically conductive diffusion barrier comprises providing a substrate in a reaction chamber and forming a titanium silicide (TiSi) region on the substrate by alternatingly exposing the substrate to a titanium-containing precursor and a first silicon-containing precursor. The method additionally comprises forming a titanium silicon nitride (TiSiN) region on the TiSi region by alternatingly exposing the substrate to a titanium-containing precursor, a nitrogen-containing precursor and a second silicon-containing precursor. The method can optionally include, prior to forming the TiSi region, forming a titanium nitride (TiN) region by alternatingly exposing the substrate to a titanium-containing precursor and a nitrogen-containing precursor.
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公开(公告)号:US11887855B2
公开(公告)日:2024-01-30
申请号:US17223506
申请日:2021-04-06
Applicant: Applied Materials, Inc.
Inventor: Xinyu Fu , Srinivas Gandikota , Avgerinos V. Gelatos , Atif Noori , Mei Chang , David Thompson , Steve G. Ghanayem
IPC: H01L21/285 , H01L21/768 , C23C16/14 , C23C16/455 , H01L21/28 , C23C16/06 , H01L21/3205 , C23C16/02 , C23C16/34 , C23C16/42
CPC classification number: H01L21/28562 , C23C16/0272 , C23C16/06 , C23C16/14 , C23C16/345 , C23C16/42 , C23C16/4557 , C23C16/45525 , C23C16/45551 , C23C16/45553 , C23C16/45563 , C23C16/45565 , C23C16/45574 , H01L21/28088 , H01L21/28506 , H01L21/32051 , H01L21/32053 , H01L21/76877
Abstract: Provided are atomic layer deposition methods to deposit a tungsten film or tungsten-containing film using a tungsten-containing reactive gas comprising one or more of tungsten pentachloride, a compound with the empirical formula WCl5 or WCl6.
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公开(公告)号:US11688856B2
公开(公告)日:2023-06-27
申请号:US17045026
申请日:2019-04-04
Inventor: Won II Park , Won Jun Chang
IPC: H01M4/62 , H01M4/04 , H01M4/136 , H01M10/0525 , C23C16/42 , H01M4/1397 , H01M4/02
CPC classification number: H01M4/628 , C23C16/42 , H01M4/0428 , H01M4/136 , H01M4/1397 , H01M10/0525 , H01M2004/028
Abstract: The present invention relates to an electrode structure for a secondary battery comprising a potential sheath capable of suppressing a side reaction between an electrode and an electrolyte through electric potential control, and a method for manufacturing the same. The electrode structure for the secondary battery according to the present invention uses the electric potential control so that an unstable SEI layer, which causes decrease in cycle characteristic and capacity of an anode material, occurs only on the surface of a potential sheath without occurring on the surface of the anode active material, thereby being capable of completely solving the problems of the existing nanostructured electrode.
The electrode structure of the present invention exhibits very excellent cycle performance that is difficult to predict from the conventional nanowire electrode structure by virtue of a synergistic effect of the potential sheath and the nanowire anode active material, and has an effect that is stable upon charging and discharging with high rate and can exert stable performance even if small cracks occur on the potential sheath.-
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公开(公告)号:US20190245044A1
公开(公告)日:2019-08-08
申请号:US16333308
申请日:2017-06-05
Applicant: SUMITOMO ELECTRIC INDUSTRIES, LTD.
Inventor: Tsutomu HORI
CPC classification number: H01L29/1608 , C23C16/325 , C23C16/42 , C30B25/20 , C30B29/36 , H01L21/02378 , H01L21/02529 , H01L21/20 , H01L21/205 , H01L29/045 , H01L29/12 , H01L29/161 , H01L29/78
Abstract: A silicon carbide epitaxial substrate includes a silicon carbide single-crystal substrate having a diameter of 100 mm or larger and including a principal surface inclined at an angle of more than 0 degrees and not less than 8 degrees with respect to a {0001} plane, a silicon carbide epitaxial layer formed on the principal surface and having a thickness of 20 μm or thicker, and a basal plane dislocation contained in the silicon carbide epitaxial layer and having one end coupled to a threading screw dislocation contained in the silicon carbide epitaxial layer and the other end present in a surface of the silicon carbide epitaxial layer. The basal plane dislocation extends in a direction having a slope of 20 degrees or more and 80 degrees or less with respect to a direction in a {0001} basal plane. Density of the basal plane dislocation is 0.05/cm2 or less.
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8.
公开(公告)号:US20180245202A1
公开(公告)日:2018-08-30
申请号:US15953961
申请日:2018-04-16
Applicant: G & H Technologies, LLC
Inventor: Vladimir GOROKHOVSKY , Brad B. HECKERMAN , Yuhang CHENG
IPC: C23C14/06 , C23C16/56 , C23C16/42 , C21D6/00 , C22C14/00 , C22C19/03 , C22C38/00 , C23C16/38 , C23C16/34 , C23C16/32 , C23C16/28 , C23C16/26 , C23C16/24 , C23C16/06 , C23C16/02 , C23C14/58 , C23C14/14 , C23C14/02 , C23C8/36 , C23C8/24 , C23C8/20 , C23C8/02 , C22F1/18 , C22F1/10 , C22C38/50 , C22C38/44 , C22C38/42 , C22C38/22 , C22C38/20 , C22C38/06 , C22C38/04 , C22C38/02 , A61B17/16 , A61C3/02 , A61C5/42
CPC classification number: C23C14/0641 , A61B17/1615 , A61B2017/1602 , A61C3/02 , A61C5/42 , C21D6/004 , C21D6/005 , C21D6/008 , C22C14/00 , C22C19/03 , C22C38/001 , C22C38/002 , C22C38/02 , C22C38/04 , C22C38/06 , C22C38/20 , C22C38/22 , C22C38/42 , C22C38/44 , C22C38/50 , C22F1/10 , C22F1/183 , C23C8/02 , C23C8/20 , C23C8/24 , C23C8/36 , C23C14/021 , C23C14/022 , C23C14/024 , C23C14/025 , C23C14/0605 , C23C14/0611 , C23C14/0635 , C23C14/067 , C23C14/0676 , C23C14/0682 , C23C14/14 , C23C14/5806 , C23C14/5826 , C23C14/586 , C23C14/588 , C23C16/0227 , C23C16/0236 , C23C16/0272 , C23C16/0281 , C23C16/06 , C23C16/24 , C23C16/26 , C23C16/28 , C23C16/32 , C23C16/34 , C23C16/38 , C23C16/42 , C23C16/56 , Y10T428/24975 , Y10T428/252 , Y10T428/265 , Y10T428/30
Abstract: A low friction top coat over a multilayer metal/ceramic bondcoat provides a conductive substrate, such as a rotary tool, with wear resistance and corrosion resistance. The top coat further provides low friction and anti-stickiness as well as high compressive stress. The high compressive stress provided by the top coat protects against degradation of the tool due to abrasion and torsional and cyclic fatigue. Substrate temperature is strictly controlled during the coating process to preserve the bulk properties of the substrate and the coating. The described coating process is particularly useful when applied to shape memory alloys.
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公开(公告)号:US20180226246A1
公开(公告)日:2018-08-09
申请号:US15325728
申请日:2014-10-14
Applicant: Mitsubishi Electric Corporation
Inventor: Kenichi HAMANO , Ryo HATTORI , Takuyo NAKAMURA
CPC classification number: H01L21/02378 , C23C16/42 , C30B29/36 , G01B9/02084 , G01B11/0625 , H01L21/02447 , H01L21/02502 , H01L21/02529 , H01L21/02576 , H01L22/12
Abstract: The present invention is aimed at providing a method of manufacturing a silicon carbide epitaxial wafer by which a plurality of silicon carbide epitaxial layers of a predetermined layer thickness can be precisely formed. In the present invention, a first n-type SiC epitaxial layer is formed on an n-type SiC substrate so that the rate of change in impurity concentration between the n-type SiC substrate and the first n-type SiC epitaxial layer will be greater than or equal to 20%. A second n-type SiC epitaxial layer is formed on the first n-type SiC epitaxial layer so that the rate of change in impurity concentration between the first n-type SiC epitaxial layer and the second n-type SiC epitaxial layer will be greater than or equal to 20%.
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公开(公告)号:US09981286B2
公开(公告)日:2018-05-29
申请号:US15064404
申请日:2016-03-08
Applicant: ASM IP HOLDING B.V.
Inventor: Jacob Huffman Woodruff , Michael Eugene Givens , Bed Sharma , Petri Räisänen
CPC classification number: B05D1/60 , B05D2203/30 , C23C16/04 , C23C16/42 , C23C16/45525 , H01L21/285
Abstract: Processes are provided for selectively depositing a metal silicide material on a first H-terminated surface of a substrate relative to a second, different surface of the same substrate. In some aspects, methods of forming a metal silicide contact layer for use in integrated circuit fabrication are provided.
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