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公开(公告)号：US20080273400A1
公开(公告)日：2008-11-06
申请号：US12113692
申请日：2008-05-01
申请人： Francesco La Rosa , Antonino Conte
发明人： Francesco La Rosa , Antonino Conte
IPC分类号： G11C16/06
CPC分类号： G11C16/225 , G11C16/102
摘要： A method writes data in a non-volatile memory comprising a main memory area comprising target locations, and an auxiliary memory area comprising auxiliary locations. The method comprises a write-erase cycle comprising: reading an initial set of data in a source location located in the main or auxiliary memory area; inserting the piece of data to be written into the initial set of data, to obtain an updated set of data, partially erasing a first group of auxiliary locations and a group of target locations designated by locations of a second group of auxiliary locations, and writing, in an erased auxiliary location of a third group of auxiliary locations, the updated set of data and the address of the target location. The method is particularly applicable to FLASH memories.
摘要翻译： 一种方法将数据写入非易失性存储器，包括包括目标位置的主存储区域和包括辅助位置的辅助存储区域。 该方法包括写擦除周期，包括：在位于主或辅助存储器区域的源位置读取初始数据集; 将待写入的数据片段插入到初始数据集中，以获得更新的数据集，部分地擦除辅助位置的第一组和由第二组辅助位置的位置指定的一组目标位置，以及写入 在第三组辅助位置的擦除辅助位置中，更新的数据集和目标位置的地址。 该方法特别适用于闪速存储器。
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32.发明申请Electrically word-erasable non-volatile memory device, and biasing method thereof 有权电可擦除非易失性存储器件及其偏置方法公开(公告)号：US20050195654A1
公开(公告)日：2005-09-08
申请号：US11067478
申请日：2005-02-25
摘要： A memory device formed by an array of memory cells extending in rows and columns. The device is formed by a plurality of N-type wells extending parallel to the rows; each N-type well houses a plurality of P-type wells extending in a direction transverse to the rows. A plurality of main bitlines extend along the columns. Each P-type well is associated to a set of local bitlines that extend along the respective P-type well and are coupled to the drain terminals of the cells accommodated in the respective P-type well. Local-bitlines managing circuits are provided for each P-type well and are located between the main bitlines and a respective set of local bitlines for controllably connecting each local bitline to a respective main bitline.
摘要翻译： 由存储单元阵列形成的存储器件，其以行和列的形式延伸。 该装置由平行于行的多个N型阱形成; 每个N型井容纳沿横向于行的方向延伸的多个P型井。 多个主位线沿着列延伸。 每个P型阱与沿着相应P型阱延伸的一组本地位线相关联，并且耦合到容纳在相应P型阱中的单元的漏极端子。 为每个P型阱提供局部位线管理电路，并且位于主位线之间，并且位于相应的一组本地位线之间，用于可控地将每个本地位线连接到相应的主位线。
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33.发明授权Sensing circuitry for reading and verifying the contents of electrically programmable and erasable non-volatile memory cells, useful in low supply-voltage technologies 有权用于读取和验证电可编程和可擦除非易失性存储器单元的内容的感测电路，可用于低电源电压技术公开(公告)号：US06906957B2
公开(公告)日：2005-06-14
申请号：US10662151
申请日：2003-09-12
CPC分类号： G11C16/28
摘要： Sensing circuitry for reading and verifying the contents of electrically programmable and erasable non-volatile memory cells, comprises a sense amplifier having a first sensing circuit portion connected to a cell to be read and provided with an output terminal for connection to a first input terminal of a comparator, and having a second reference circuit portion connected to a reference current generator and provided with an output terminal for connection to a second input terminal of said comparator, characterized in that said first and said second circuit portions comprise a series of first and second transistors, respectively, being connected between a first voltage reference and a second voltage reference and having respective points of interconnection connected to said output terminals of said first and second circuit portions.
摘要翻译： 用于读取和验证电可编程和可擦除非易失性存储单元的内容的感测电路包括读出放大器，其具有连接到要读取的单元的第一感测电路部分，并且具有用于连接到第一输入端的第一输入端的输出端 比较器，并具有连接到参考电流发生器的第二参考电路部分，并且具有用于连接到所述比较器的第二输入端子的输出端子，其特征在于，所述第一和所述第二电路部分包括一系列第一和第二 晶体管分别连接在第一参考电压和第二电压基准之间，并且具有连接到所述第一和第二电路部分的所述输出端子的互连互连点。
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34.发明申请Low-consumption regulator for a charge pump voltage generator and related system and method 有权低耗电调节器用于电荷泵电压发生器及相关系统及方法公开(公告)号：US20050030771A1
公开(公告)日：2005-02-10
申请号：US10877063
申请日：2004-06-24
申请人： Antonino Conte , Enrico Castaldo
发明人： Antonino Conte , Enrico Castaldo
CPC分类号： H02M3/073
摘要： A regulator circuit for a charge pump voltage generator comprises a voltage comparator means for performing a voltage comparison between a charge pump output voltage and a reference voltage, and means responsive to the voltage comparator means for conditioning a charge pump clocking to the result of the voltage comparison. The voltage comparator means includes sampling means for sampling the charge pump output voltage at a sampling rate. Sampling rate control means are provided, responsive to the voltage comparison, for controlling the sampling rate according to the result of the voltage comparison.
摘要翻译： 用于电荷泵电压发生器的调节器电路包括用于执行电荷泵输出电压和参考电压之间的电压比较的电压比较器装置，以及响应于电压比较器装置的装置，用于调节针对电压的结果的电荷泵时钟 比较。 电压比较器装置包括用于以采样率对电荷泵输出电压进行采样的采样装置。 提供响应于电压比较的采样率控制装置，用于根据电压比较的结果来控制采样率。
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公开(公告)号：US06680643B2
公开(公告)日：2004-01-20
申请号：US10060870
申请日：2002-01-30
申请人： Antonino Conte , Oreste Concepito
发明人： Antonino Conte , Oreste Concepito
IPC分类号： G05F110
CPC分类号： G05F3/30
摘要： Bandgap type reference voltage source using an operational transimpedance amplifier. The bandgap stage is formed by a first and a second bandgap branch parallel-connected; the first bandgap branch comprises a first diode and a transistor, series-connected and forming a first output node; the second bandgap branch comprises a second diode and a second transistor series-connected and forming a second output node. The operational amplifier has inputs connected to the output nodes of the bandgap stage. An amplifier current detecting stage is connected to the outputs of the operational amplifier and supplies a current related to the current drawn by the operational amplifier. A diode current detecting stage is connected to the output of the amplifier current detecting stage and to an output of the operational amplifier and supplies a current related to the current flowing in the first diode. An output stage transforms this current into a stabilized voltage.
摘要翻译： 带隙型参考电压源，采用运算跨阻放大器。 带隙级由并联的第一和第二带隙分支形成; 第一带隙分支包括串联连接并形成第一输出节点的第一二极管和晶体管; 第二带隙分支包括串联连接并形成第二输出节点的第二二极管和第二晶体管。 运算放大器具有连接到带隙级的输出节点的输入。 放大器电流检测级连接到运算放大器的输出，并提供与运算放大器所绘制的电流相关的电流。 二极管电流检测级连接到放大器电流检测级的输出端和运算放大器的输出，并提供与流过第一二极管的电流相关的电流。 输出级将该电流转换成稳定的电压。
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公开(公告)号：US08902678B2
公开(公告)日：2014-12-02
申请号：US13405619
申请日：2012-02-27
CPC分类号： G05F1/575 , Y10T29/49117
摘要： A voltage regulator may include an input terminal for receiving an input voltage and an output terminal for providing a respective output voltage, a regulation transistor having a first conduction terminal coupled to the input terminal for receiving the input voltage, a second conduction terminal coupled to the output terminal, and a control terminal coupled to the output of a first operational amplifier. The first operational amplifier may have a non-inverting input terminal for receiving a first reference voltage, and an inverting input terminal coupled to a first terminal of a divider circuit for receiving a second reference voltage.
摘要翻译： 电压调节器可以包括用于接收输入电压的输入端子和用于提供相应输出电压的输出端子;调节晶体管，其具有耦合到输入端子的第一导电端子用于接收输入电压;第二导通端子， 输出端子和耦合到第一运算放大器的输出端的控制端子。 第一运算放大器可以具有用于接收第一参考电压的非反相输入端子，以及耦合到用于接收第二参考电压的除法器电路的第一端子的反相输入端子。
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37.发明授权Dynamic biasing circuit for a protection stage using low voltage transistors 有权用于使用低压晶体管的保护级的动态偏置电路公开(公告)号：US08604868B2
公开(公告)日：2013-12-10
申请号：US13435210
申请日：2012-03-30
IPC分类号： G05F1/10
CPC分类号： H03K17/102 , H03K3/356113
摘要： A biasing circuit may include an input configured to receive a supply voltage, a value of which is higher than a limit voltage. The biasing circuit may also include a control stage configured to generate first and second control signals with mutually complementary values, equal alternatively to a first value, in a first half-period of a clock signal, or to a second value, in a second half-period of the clock signal. The first and second values may be a function of the supply and limit voltages. The biasing circuit may also include a biasing stage configured to generate a biasing voltage as a function of the values of the first and second control signals. The first and second control signals may control transfer transistors for transferring the supply voltage to respective outputs, while the biasing voltage may be for controlling protection transistors to reduce overvoltages on the transfer transistors.
摘要翻译： 偏置电路可以包括被配置为接收其值高于限制电压的电源电压的输入。 偏置电路还可以包括控制级，其被配置为在时钟信号的第一半个周期中产生第二和第二控制信号，该第一和第二控制信号具有相互互补的值，等于第一个值，或在第二个半个时钟信号中的第二个值 时钟信号的周期。 第一和第二值可以是电源和极限电压的函数。 偏置电路还可以包括被配置为产生作为第一和第二控制信号的值的函数的偏置电压的偏置级。 第一和第二控制信号可以控制用于将电源电压传送到各个输出的转移晶体管，而偏置电压可以用于控制保护晶体管以减小转移晶体管的过电压。
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38.发明授权Circuit for generating a reference voltage with compensation of the offset voltage 有权用于产生具有补偿偏移电压的参考电压的电路公开(公告)号：US08482342B2
公开(公告)日：2013-07-09
申请号：US12913682
申请日：2010-10-27
CPC分类号： G05F3/30 , H03F3/347 , H03F3/45183 , H03F2203/45466
摘要： An embodiment of a circuit includes first and second branches, an amplifier, a compensation circuit, and a bias unit. The first and second branches are respectively operable to generate first and second currents. The amplifier has a first amplifier input node coupled to the first branch, a second amplifier input node coupled to the second branch, an amplifier output node coupled to the first and second branches, and a first compensation node. The compensation unit is operable to provide a first offset-compensation signal to the first compensation node. And the first bias unit is operable to provide first and second bias signals to the first and second input nodes, respectively, such that the amplifier is operable to cause the first current to approximately equal the second current.
摘要翻译： 电路的一个实施例包括第一和第二分支，放大器，补偿电路和偏置单元。 第一和第二分支分别可操作以产生第一和第二电流。 放大器具有耦合到第一分支的第一放大器输入节点，耦合到第二分支的第二放大器输入节点，耦合到第一和第二分支的放大器输出节点和第一补偿节点。 补偿单元可操作以向第一补偿节点提供第一偏移补偿信号。 并且第一偏置单元可操作以分别向第一和第二输入节点提供第一和第二偏置信号，使得放大器可操作以使第一电流近似等于第二电流。
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公开(公告)号：US20120002473A1
公开(公告)日：2012-01-05
申请号：US13170657
申请日：2011-06-28
IPC分类号： G11C16/10
摘要： An electronic device including a set of functional block, and a biasing block for generating a set of bias voltages for the functional blocks. The electronic device further includes a holding block coupled between the biasing block and the functional blocks for providing each bias voltage to at least one corresponding functional block, for each bias voltage the holding block including a capacitive element for storing the bias voltage, and a switch element switchable between an accumulation condition wherein provides the bias voltage from the biasing block to the capacitive element and to the at least one corresponding functional block, and a release condition wherein isolates the capacitive element from the biasing block and provides the bias voltage from the capacitive element to the at least one corresponding functional block, and a control block for alternately switching the switching elements between the accumulation condition and the release condition.
摘要翻译： 一种包括一组功能块的电子设备和用于产生用于功能块的一组偏置电压的偏置块。 该电子设备还包括一个保持块，该保持块耦合在偏置块和功能块之间，用于将每个偏置电压提供给至少一个对应的功能块，对于每个偏置电压，保持块包括用于存储偏置电压的电容元件，以及开关 元件可在其中提供从偏置块到电容元件的偏置电压到至少一个对应的功能块的累积条件之间切换，以及释放条件，其中将电容元件与偏置块隔离并提供来自电容 元件到所述至少一个对应的功能块，以及用于在所述累积条件和所述释放条件之间交替地切换所述开关元件的控制块。
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40.发明申请METHOD FOR BIASING AN EEPROM NON-VOLATILE MEMORY ARRAY AND CORRESPONDING EEPROM NON-VOLATILE MEMORY DEVICE 有权用于偏移EEPROM非易失性存储器阵列和对应EEPROM非易失性存储器件的方法公开(公告)号：US20110068179A1
公开(公告)日：2011-03-24
申请号：US12885028
申请日：2010-09-17
IPC分类号： G06K19/073 , G11C16/14 , G11C16/12
CPC分类号： G11C16/0433 , G11C16/10 , G11C16/16
摘要： Described herein is a method for biasing an EEPROM array formed by memory cells arranged in rows and columns, each operatively coupled to a first switch and to a second switch and having a first current-conduction terminal selectively connectable to a bitline through the first switch and a control terminal selectively connectable to a gate-control line through the second switch, wherein associated to each row are a first wordline and a second wordline, connected to the control terminals of the first switches and, respectively, of the second switches operatively coupled to the memory cells of the same row. The method envisages selecting at least one memory cell for a given memory operation, biasing the first wordline and the second wordline of the row associated thereto, and in particular biasing the first and second wordlines with voltages different from one another and having values that are higher than an internal supply voltage and are a function of the given memory operation.
摘要翻译： 这里描述了一种用于偏置由排列成行和列的存储器单元形成的EEPROM阵列的方法，每个可操作地耦合到第一开关和第二开关，并且具有通过第一开关选择性地连接到位线的第一导通端子， 选择性地可连接到通过第二开关的栅极控制线的控制终端，其中与每一行相关联的是分别连接到第一开关的控制端的第一字线和第二字线，以及分别操作地耦合到 同一行的存储单元。 该方法设想为给定的存储器操作选择至少一个存储器单元，偏置与其相关联的行的第一字线和第二字线，并且特别是以彼此不同的电压偏置第一和第二字线并且具有更高的值 而不是内部电源电压，并且是给定存储器操作的函数。
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