公开(公告)号：US20250111591A1

公开(公告)日：2025-04-03

申请号：US18978482

申请日：2024-12-12

Applicant: Apple Inc.

Inventor： Ali Rabbani Rankouhi ,  Christopher A. Burns ,  Justin A. Hensley ,  Luca Iuliano ,  Jonathan M. Redshaw

IPC: G06T15/06 ,  G06F9/38 ,  G06F9/48 ,  G06F9/50 ,  G06F16/22 ,  G06F30/31 ,  G06Q10/101 ,  G06Q50/04 ,  G06T1/20 ,  G06T1/60 ,  G06T15/00 ,  G06T17/00 ,  G06T17/10 ,  G16H40/67

Abstract: Disclosed techniques relate to traversal techniques for ray tracing. In some embodiments, ray intersect circuitry receives a ray intersect request that indicates origin and direction information for a ray in a graphics scene. The ray intersect circuitry may traverse multiple nodes of a spatially organized acceleration data structure, wherein a given node of the multiple nodes indicates coordinates corresponding to a bounding region of the graphics scene. In response to detection that the ray intersects with a first bounding volume, the ray intersect circuitry stores a local parametric value for the ray that indicates a point at which the ray intersected the first bounding volume and may use the local parametric value as an origin value of the ray for one or more intersection tests between the ray and one or more child bounding volumes of the first bounding volume.

公开(公告)号：US20240404172A1

公开(公告)日：2024-12-05

申请号：US18329055

申请日：2023-06-05

Applicant: Apple Inc.

Inventor： Christopher A. Burns ,  Casper R. van Benthem

IPC: G06T15/06 ,  G06T15/00

Abstract: Techniques are disclosed relating to ray intersection tests for ray tracing in graphics processors. In some embodiments, a ray cache stores, transformed ray direction corresponding to a transform of a ray based on its dominant direction axis. Ray intersect acceleration circuitry may determine whether a ray intersects a bounding volume of a bounding volume hierarchy (BVH) data structure. Ray-plane test circuitry may perform a set of six ray-plane tests for the bounding volume using at most four floating-point multiplication operations by four multiplier circuits. The floating-point operations may operate on the transformed ray direction components from the ray cache circuitry and coordinate information for the bounding volume. Disclosed techniques may reduce area and power consumption by avoiding multiplier circuitry for some ray-plane tests.

公开(公告)号：US11875448B2

公开(公告)日：2024-01-16

申请号：US17103382

申请日：2020-11-24

Applicant: Apple Inc.

Inventor： Ali Rabbani Rankouhi ,  Christopher A. Burns ,  Justin A. Hensley ,  Jonathan M. Redshaw

IPC: G06T15/06 ,  G06F30/31 ,  G06T15/00 ,  G06F9/48 ,  G06F9/50 ,  G06T1/20 ,  G06F16/22 ,  G06F9/38 ,  G06T1/60 ,  G06T17/00 ,  G16H40/67 ,  G06Q10/101 ,  G06Q50/04

CPC classification number: G06T15/06 ,  G06F9/3887 ,  G06F9/4881 ,  G06F9/5016 ,  G06F9/5027 ,  G06F16/2246 ,  G06F30/31 ,  G06T1/20 ,  G06T1/60 ,  G06T15/005 ,  G06T17/005 ,  G06Q10/101 ,  G06Q50/04 ,  G06T17/00 ,  G06T2210/12 ,  G06T2210/21 ,  G16H40/67

Abstract: Disclosed techniques relate to forming single-instruction multiple-data (SIMD) groups during ray intersection traversal. In particular, ray intersection circuitry may include dedicated circuitry configured to traverse an acceleration data structure, but may dynamically form a SIMD group to transform ray coordinates when traversing from one level of the data structure to another. This may allow shader processors to execute the SIMD group to perform the transformation. Disclosed techniques may facilitate instancing of graphics models within the acceleration data structure.

公开(公告)号：US20230102071A1

公开(公告)日：2023-03-30

申请号：US17456483

申请日：2021-11-24

Applicant: Apple Inc.

Inventor： Christopher A. Burns

IPC: G06T15/06

Abstract: Techniques are disclosed relating to primitive intersection testing for ray tracing in graphics processors. In some embodiments, a graphics processor includes ray intersection circuitry configured to perform an intersection test, which includes to: quantize a first representation of the primitive to generate a reduced-precision interval representation of the primitive, quantize a first representation of the ray to generate a reduced-precision interval representation of the ray, and determine, using interval arithmetic, an initial intersection result based on coordinates of the interval representation of the primitive and coordinates of the interval representation of the ray. The initial intersection result may be a conservative result such that a miss indicated by the initial intersection result is guaranteed not to be a hit for the first representation of the primitive and first representation of the ray. Disclosed techniques may improve performance, reduce power consumption, or both, relative to traditional techniques.

公开(公告)号：US20220207690A1

公开(公告)日：2022-06-30

申请号：US17136542

申请日：2020-12-29

Applicant: Apple Inc.

Inventor： Christopher A. Burns ,  Casper R. W. van Benthem

IPC: G06T7/00 ,  G06T15/06 ,  G06T15/00 ,  G06T17/10 ,  G06T1/20

Abstract: Techniques are disclosed relating to testing whether a ray intersects a graphics primitive, e.g., for ray tracing. In some embodiments, intersection circuitry performs a reduced-precision conservative intersection test and shader circuitry performs an original-precision intersection test if the intersection circuitry indicates a hit. The intersection circuitry may quantize the ray (and may quantize the primitive or may receive a quantized representation of the primitive) and generates a potential error value based on propagation of quantization error for the primitive and ray. The intersection circuitry then determines an intersection result for the reduced-precision test based on the quantized primitive data and the potential error. In various embodiments, disclosed techniques may improve performance or reduce power consumption by reducing the number of original-precision intersection tests that do not result in hits.

公开(公告)号：US20220036652A1

公开(公告)日：2022-02-03

申请号：US17103352

申请日：2020-11-24

Applicant: Apple Inc.

Inventor： Ali Rabbani Rankouhi ,  Christopher A. Burns ,  Justin A. Hensley

IPC: G06T17/10 ,  G06T15/06 ,  G06T15/00 ,  G06T1/20

Abstract: Disclosed techniques relate to an acceleration data structure for ray intersection with a many-to-many mapping between bounding regions and primitives. In some embodiments, one or more graphics processors access data for multiple graphics primitives in a graphics scene and generate a spatially organized data structure. Some nodes of the data structure indicate graphics primitives and some nodes indicate coordinates of bounding regions in the graphics scene. In some embodiments, the spatially organized data structure includes a node with a bounding region for which multiple primitives are indicated as children and also includes a primitive for which multiple bounding regions are indicated as parents. Disclosed techniques may generate bounding regions that closely fit primitives, which may reduce primitive testing for ray tracing. This in turn may increase performance or reduce power consumption relative to traditional techniques.

公开(公告)号：US20220036638A1

公开(公告)日：2022-02-03

申请号：US17103406

申请日：2020-11-24

Applicant: Apple Inc.

Inventor： Ali Rabbani Rankouhi ,  Christopher A. Burns ,  Justin A. Hensley ,  Luca Iuliano ,  Jonathan M. Redshaw

IPC: G06T15/06 ,  G06T15/00

Abstract: Disclosed techniques relate to primitive testing associated with ray intersection processing for ray tracing. In some embodiments, shader circuitry executes a first SIMD group that includes a ray intersect instruction for a set of rays. Ray intersect circuitry traverses, in response to the ray intersect instruction, multiple nodes in a spatially organized acceleration data structure (ADS). In response to reaching a node of the ADS that indicates one or more primitives, the apparatus forms a second SIMD group that executes one or more instructions to determine whether a set of rays that have reached the node intersect the one or more primitives. The shader circuitry may execute the first SIMD group to shade one or more primitives that are indicated as intersected based on results of execution of the second SIMD group. Thus, disclosed techniques may use both dedicated ray intersect circuitry and dynamically formed SIMD groups executed by shader processors to detect ray intersection.

公开(公告)号：US20210149679A1

公开(公告)日：2021-05-20

申请号：US16686060

申请日：2019-11-15

Applicant: Apple Inc.

Inventor： Christopher A. Burns ,  Liang-Kai Wang ,  Robert D. Kenney ,  Terence M. Potter

IPC: G06F9/38 ,  G06F9/30 ,  G06T1/20 ,  G06T1/60

Abstract: Techniques are disclosed relating to operand routing among SIMD pipelines. In some embodiments, an apparatus includes a set of multiple hardware pipelines configured to execute a single-instruction multiple-data (SIMD) instruction for multiple threads in parallel, wherein the instruction specifies first and second architectural registers. In some embodiments, the pipelines include execution circuitry configured to perform operations using one or more pipeline stages of the pipeline. In some embodiments, the pipelines include routing circuitry configured to select, based on the instruction, a first input operand for the execution circuitry from among: a value from the first architectural register from thread-specific storage for another pipeline and a value from the second architectural register from thread-specific storage for a thread assigned to another pipeline. In some embodiments, the routing circuitry may support a shift and fill instruction that facilitates storage of an arbitrary portion of a graphics frame in one or more registers.

公开(公告)号：US10282169B2

公开(公告)日：2019-05-07

申请号：US15092401

申请日：2016-04-06

Applicant: Apple Inc.

Inventor： Liang-Kai Wang ,  Terence M. Potter ,  Andrew M. Havlir ,  Yu Sun ,  Nicolas X. Pena ,  Xiao-Long Wu ,  Christopher A. Burns

IPC: G06F7/483 ,  G06F7/544

Abstract: Techniques are disclosed relating to floating-point operations with down-conversion. In some embodiments, a floating-point unit is configured to perform fused multiply-addition operations based on first and second different instruction types. In some embodiments, the first instruction type specifies result in the first floating-point format and the second instruction type specifies fused multiply addition of input operands in the first floating-point format to generate a result in a second, lower-precision floating-point format. For example, the first format may be a 32-bit format and the second format may be a 16-bit format. In some embodiments, the floating-point unit includes rounding circuitry, exponent circuitry, and/or increment circuitry configured to generate signals for the second instruction type in the same pipeline stage as for the first instruction type. In some embodiments, disclosed techniques may reduce the number of pipeline stages included in the floating-point circuitry.

公开(公告)号：US10192349B2

公开(公告)日：2019-01-29

申请号：US15870081

申请日：2018-01-12

Applicant: Apple Inc.

Inventor： Christopher A. Burns ,  Justin A. Hensley

IPC: G06T15/00 ,  G06T15/04 ,  G06T15/06

Abstract: Techniques are disclosed relating to texture sampling operations. In some embodiments, multi-fetch sampling instructions specify a region of a texture in which multiple samples are to be performed and texture processing circuitry is configured to sample the texture multiple times within the region. In some embodiments, the locations of the samples are determined according to a formula, which may be pseudo-random. In some embodiments, the locations of the samples are jittered to produce stochastic results. In some embodiments, the locations of the samples are determined based on one or more stored sets of samples that have particular properties (e.g., blue noise, in some embodiments). In various embodiments, disclosed techniques may facilitate Monte Carlo sampling.