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公开(公告)号：US10657619B2
公开(公告)日：2020-05-19
申请号：US15612796
申请日：2017-06-02
Applicant: Apple Inc.
Inventor： Michal Valient , Sean P. James , Gokhan Avkarogullari , Alexander K. Kan , Michael Imbrogno
Abstract: The disclosure pertains to techniques for operation of graphics systems and task execution on a graphics processor. One such technique comprises a computer-implemented method for task execution on a graphics processor, the method comprising creating a data structure for grouping data resources, populating the data structure with two or more data resources for encoding into a graphics processing language by an encoding object, passing the data structure to a first programming interface command, the first programming interface command configured to access the data structure's data resources, triggering execution of a first function on a graphics processor in response to passing the data structure to the first programming interface command, passing the data structure to a second programming interface command, the second programming interface command configured to access the data structure's data resources, and triggering execution of a second function on the graphics processor in response to passing the data structure to the second programming interface command.
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公开(公告)号：US10269167B1
公开(公告)日：2019-04-23
申请号：US15984931
申请日：2018-05-21
Applicant: Apple Inc.
Inventor： Michael Imbrogno , Michal Valient
Abstract: Systems, methods, and computer readable media to encode and execute an indirect command buffer are described. A processor creates an indirect command buffer that is configured to be encoded into by a graphics processor at a later point in time. The processor encodes, within a command buffer, a produce command that references the indirect command buffer, where the produce command triggers execution on the graphics processor a first operation that encodes a set of commands within the data structure. The processor also encodes, within the command buffer, a consume command that triggers execution on the graphics processor a second operation that executes the set of commands encoded within the data structure. After encoding the command buffer, a processor commits the command buffer for execution on the graphics processor.
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公开(公告)号：US20180350029A1
公开(公告)日：2018-12-06
申请号：US15612796
申请日：2017-06-02
Applicant: Apple Inc.
Inventor： Michal Valient , Sean P. James , Gokhan Avkarogullari , Alexander K. Kan , Michael Imbrogno
CPC classification number: G06F9/4484
Abstract: The disclosure pertains to techniques for operation of graphics systems and task execution on a graphics processor. One such technique comprises a computer-implemented method for task execution on a graphics processor, the method comprising creating a data structure for grouping data resources, populating the data structure with two or more data resources for encoding into a graphics processing language by an encoding object, passing the data structure to a first programming interface command, the first programming interface command configured to access the data structure's data resources, triggering execution of a first function on a graphics processor in response to passing the data structure to the first programming interface command, passing the data structure to a second programming interface command, the second programming interface command configured to access the data structure's data resources, and triggering execution of a second function on the graphics processor in response to passing the data structure to the second programming interface command.
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公开(公告)号：US20180182154A1
公开(公告)日：2018-06-28
申请号：US15388985
申请日：2016-12-22
Applicant: Apple Inc.
Inventor： Terence M. Potter , Richard W. Schreyer , James J. Ding , Alexander K. Kan , Michael Imbrogno
CPC classification number: G06T15/005
Abstract: Techniques are disclosed relating to synchronizing access to pixel resources. Examples of pixel resources include color attachments, a stencil buffer, and a depth buffer. In some embodiments, hardware registers are used to track status of assigned pixel resources and pixel wait and pixel release instruction are used to synchronize access to the pixel resources. In some embodiments, other accesses to the pixel resources may occur out of program order. Relative to tracking and ordering pass groups, this weak ordering and explicit synchronization may improve performance and reduce power consumption. Disclosed techniques may also facilitate coordination between fragment rendering threads and auxiliary mid-render compute tasks.
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