公开(公告)号：US11094036B2

公开(公告)日：2021-08-17

申请号：US16850101

申请日：2020-04-16

Applicant: Apple Inc.

Inventor： Michal Valient ,  Sean P. James ,  Gokhan Avkarogullari ,  Alexander K. Kan ,  Michael Imbrogno

IPC: G06T1/60 ,  G06F3/14 ,  G06T1/20 ,  G09G5/36 ,  G06T15/00 ,  G06T15/04 ,  G06F9/448

Abstract: The disclosure pertains to techniques for operation of graphics systems and task execution on a graphics processor. One such technique comprises a computer-implemented method for task execution on a graphics processor, the method comprising creating a data structure for grouping data resources, populating the data structure with two or more data resources for encoding into a graphics processing language by an encoding object, passing the data structure to a first programming interface command, the first programming interface command configured to access the data structure's data resources, triggering execution of a first function on a graphics processer in response to passing the data structure to the first programming interface command, passing the data structure to a second programming interface command, the second programming interface command configured to access the data structure's data resources, and triggering execution of a second function on the graphics processer in response to passing the data structure to the second programming interface command.

公开(公告)号：US10672099B2

公开(公告)日：2020-06-02

申请号：US15996312

申请日：2018-06-01

Applicant: Apple Inc.

Inventor： Michael Imbrogno ,  Ryan D. Schmitt

IPC: G06T1/20 ,  G06T1/60 ,  G06F12/0802 ,  G06F9/50 ,  G06F12/0891

Abstract: Systems, methods, and computer readable media to manage memory cache for graphics processing are described. A processor creates a resource group for a plurality of graphics application program interface (API) resources. The processor subsequently encodes a set command that references the resource group within a command buffer and assigns a data set identifier (DSID) to the resource group. The processor also encodes a write command within the command buffer that causes the graphics processor to write data within a cache line and mark the written cache line with the DSID, a read command that causes the graphics processor to read data written into the resource group, and a drop command that causes the graphics processor to notify the memory cache to drop, without flushing to memory, data stored within the cache line.

公开(公告)号：US10319068B2

公开(公告)日：2019-06-11

申请号：US15587063

申请日：2017-05-04

Applicant: Apple Inc.

Inventor： Michael J. Swift ,  Michael Imbrogno ,  Gokhan Avkarogullari

IPC: G06T1/00 ,  G06T1/60 ,  G06T1/20 ,  G06T15/00

Abstract: One disclosed embodiment includes memory allocation methods for use by a graphics processing unit in rendering graphics data for display. The method includes receiving a buffer attachment associated with a first rendering pass. The hardware prerequisites for operation of the first rendering pass is determined. The method also includes receiving an indication to not allocate system memory for the received buffer attachment. Thereafter, it may be determined whether the received buffer attachment will be loaded from or stored to by the subsequent rendering passes. If it is determined that the buffer attachment will be accessed by the subsequent rendering passes, an error message may be generated indicating that system memory must be allocated. If it is determined that the buffer attachment will not be accessed by the subsequent rendering passes, the buffer attachment is rendered without allocating system memory.

公开(公告)号：US20170358054A1

公开(公告)日：2017-12-14

申请号：US15467268

申请日：2017-03-23

Applicant: Apple Inc.

Inventor： Bartosz Ciechanowski ,  Michael Imbrogno ,  Gokhan Avkarogullari ,  Nathaniel C. Begeman ,  Sean M. Gies ,  Michael J. Swift

IPC: G06T1/60 ,  G06T15/00 ,  G06T1/20

Abstract: One disclosed embodiment is directed to graphics processing method for displaying a user interface. The method includes executing a plurality of graphic processing operation in a single rendering pass. The rendering pass includes several render targets. At least one of the render targets is designated as a memory-less render target. The memory-less render target is used to store intermediate data. The intermediate data is combined with the outcome of at least one other graphics processing operation to generate a combined result. The combined result is stored in the frame buffer memory for display.

公开(公告)号：US11010863B2

公开(公告)日：2021-05-18

申请号：US16786173

申请日：2020-02-10

Applicant: Apple Inc.

Inventor： Michael Imbrogno ,  Sivert Berg ,  Nicholas H. Smith

IPC: G06F9/30 ,  G06T15/04 ,  G06F8/41 ,  G06T1/60 ,  G06T1/20 ,  G06F12/06

Abstract: A computer-implemented technique for accessing textures by a graphics processing unit (GPU), includes determining a frequency with which a first texture is expected to be accessed by an application executing on a GPU, determining a frequency with which a second texture is expected to be accessed by an application executing on the GPU, determining to load memory address information associated with the first texture into a GPU register when the frequency is greater than or equal to a threshold frequency value, determining to load memory address information associated with the second texture into a buffer memory when the frequency is less than the threshold frequency value, receiving a draw call utilizing the texture, rendering the draw call using the first texture by accessing the memory address information in the GPU register, and the second texture by accessing the memory address information in the buffer memory.

公开(公告)号：US20210096994A1

公开(公告)日：2021-04-01

申请号：US16783766

申请日：2020-02-06

Applicant: Apple Inc.

Inventor： Rohan Sehgal ,  Michael Imbrogno

IPC: G06F12/0837 ,  G06F12/0808 ,  G06F9/48 ,  G06F9/30 ,  G06F9/50 ,  G06F9/54 ,  G06F12/126

Abstract: Systems, methods, and computer readable media to manage memory cache for graphics processing are described. A processor creates a resource group for a plurality of graphics application program interface (API) resources. The processor subsequently encodes a set command that references the resource group within a command buffer and assigns a data set identifier (DSID) to the resource group. The processor also encodes a write command within the command buffer that causes the graphics processor to write data within a cache line and mark the written cache line with the DSID, a read command that causes the graphics processor to read data written into the resource group, and a de-prioritize command that causes the graphics processor to notify the memory cache to later flush content from the cache line associated with the DSID and to later invalidate the cache line when higher priority content is received.

公开(公告)号：US20190370929A1

公开(公告)日：2019-12-05

申请号：US15996312

申请日：2018-06-01

Applicant: Apple Inc.

Inventor： Michael Imbrogno ,  Ryan D. Schmitt

IPC: G06T1/60 ,  G06F9/50 ,  G06F12/0891 ,  G06T1/20

Abstract: Systems, methods, and computer readable media to manage memory cache for graphics processing are described. A processor creates a resource group for a plurality of graphics application program interface (API) resources. The processor subsequently encodes a set command that references the resource group within a command buffer and assigns a data set identifier (DSID) to the resource group. The processor also encodes a write command within the command buffer that causes the graphics processor to write data within a cache line and mark the written cache line with the DSID, a read command that causes the graphics processor to read data written into the resource group, and a drop command that causes the graphics processor to notify the memory cache to drop, without flushing to memory, data stored within the cache line.

公开(公告)号：US20190355163A1

公开(公告)日：2019-11-21

申请号：US16390654

申请日：2019-04-22

Applicant: Apple Inc.

Inventor： Michael Imbrogno ,  Michal Valient

IPC: G06T15/00 ,  G06T1/20 ,  G06F9/54 ,  G06T1/60

Abstract: Systems, methods, and computer readable media to encode and execute an indirect command buffer are described. A processor creates an indirect command buffer that is configured to be encoded into by a graphics processor at a later point in time. The processor encodes, within a command buffer, a produce command that references the indirect command buffer, where the produce command triggers execution on the graphics processor of a first operation that encodes a set of commands within the data structure. The processor also encodes, within the command buffer, a consume command that triggers execution on the graphics processor of a second operation that executes the set of commands encoded within the data structure. After encoding the command buffer, a processor commits the command buffer for execution on the graphics processor.

公开(公告)号：US10169887B2

公开(公告)日：2019-01-01

申请号：US15179738

申请日：2016-06-10

Applicant: Apple Inc.

Inventor： Domenico Troiano ,  Michael Imbrogno

IPC: G06T11/00 ,  G06T1/60 ,  G06T15/04

Abstract: Systems, computer readable media, and methods for hardware accelerated blits of multisampled textures on graphics processing units (GPUs) are disclosed. For multisampled surfaces, texture-to-buffer blits cannot be trivially implemented because most GPUs do not support writing multisampled surfaces with a linear memory layout. Moreover, GPUs often have a maximum limit for row stride (i.e., the number of bytes from one row of pixels in memory to the next) and/or texture size. When the destination buffer for the blit of a multisampled texture is too large to be aliased by an equivalent non-multisampled texture view, the stride of the view has no spatial relationship with the destination buffer. Thus, to access the source texture correctly, a ‘remapping’ may be performed to determine the linear sample index of a fragment within the view, and the destination buffer stride may be used to compute the texture coordinates used to sample the source texture.

公开(公告)号：US20220261290A1

公开(公告)日：2022-08-18

申请号：US17661624

申请日：2022-05-02

Applicant: Apple Inc.

Inventor： Kutty Banerjee ,  Michael Imbrogno

IPC: G06F9/50 ,  G06T1/20 ,  G06F9/48

Abstract: In general, embodiments are disclosed herein for tracking and allocating graphics hardware resources. In one embodiment, a software and/or firmware process constructs a cross-application command queue utilization table based on one or more specified command queue quality of service (QoS) settings, in order to track the target and current utilization rates of each command queue on the graphics hardware over a given frame and to load work onto the graphics hardware in accordance with the utilization table. Based on the constructed utilization table for a given frame, any command queues that have exceed their respective target utilization value may be moved to an “inactive” status for the duration of the current frame. For any command queues that remain in an “active” status for the current frame, work from those command queues may be loaded on to slots of the appropriate data masters of the graphics hardware in any desired order.