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    PROCESSING CIRCUIT HARDWARE RESOURCE ALLOCATION SYSTEM
    1.
    发明申请
    PROCESSING CIRCUIT HARDWARE RESOURCE ALLOCATION SYSTEM 审中-公开

    公开(公告)号：US20180173560A1

    公开(公告)日：2018-06-21

    申请号：US15386570

    申请日：2016-12-21

    Applicant: Apple Inc.

    Inventor： Gokhan Avkarogullari ,  Terence M. Potter ,  Benjiman L. Goodman ,  Ralph C. Taylor ,  Kutty Banerjee

    IPC: G06F9/48 ,  G06F9/50

    CPC classification number: G06F9/4818 ,  G06F9/505 ,  G06F2209/5021

    Abstract: In various embodiments, hardware resources of a processing circuit may be allocated to a plurality of processes based on priorities of the processes. A hardware resource utilization sensor may detect a current utilization of the hardware resources by a process. A utilization accumulation circuit may determine a utilization of the hardware resources by the process over a particular amount of time. A target utilization of the hardware resources for the process may be determined based on the utilization of the hardware resources over the particular amount of time. A comparator circuit may compare the current utilization to the target utilization. A process priority adjustment circuit may adjust a priority of the process based on the comparison. Based on the adjusted priority, a different amount of hardware resources may be allocated to the processes.

    Smart Dynamic Voltage and Frequency Scaling of Electronic Components
    3.
    发明申请
    Smart Dynamic Voltage and Frequency Scaling of Electronic Components 审中-公开

    公开(公告)号：US20170269666A1

    公开(公告)日：2017-09-21

    申请号：US15074780

    申请日：2016-03-18

    Applicant: Apple Inc.

    Inventor： Rohan S. Patil ,  Tatsuya Iwamoto ,  Gokhan Avkarogullari

    IPC: G06F1/32

    CPC classification number: G06F1/324 ,  G06F1/3206 ,  G06F1/3296 ,  Y02D10/126 ,  Y02D10/172

    Abstract: Techniques for managing components of a processing system are described. Illustrative components include graphics processing units (GPUs), central processing units (CPUs), communication fabrics, memory controllers, or peripheral control circuits. For one embodiment, a performance control logic/module obtains information associated with components of a system during performance of a task by the system. The logic/module can determine the need to adjust an operational performance of a first component based on the obtained information. The performance control logic/module can also evaluate the obtained information to determine that the operational performance of one or more second components of the system should be adjusted to satisfy the determined need (of the first component). Moreover, the logic/module can adjust a first clock signal affecting the operational performance of the first component and one or more second clock signals affecting the operational performance of the one or more second components.

    Combining compute tasks for a graphics processing unit
    4.
    发明授权
    Combining compute tasks for a graphics processing unit 有权
    组合图形处理单元的计算任务

    公开(公告)号：US09442706B2

    公开(公告)日：2016-09-13

    申请号：US14448927

    申请日：2014-07-31

    Applicant: Apple Inc.

    Inventor： Gokhan Avkarogullari ,  Alexander K. Kan ,  Kelvin C. Chiu

    IPC: G06F9/45 ,  G06F9/445

    CPC classification number: G06F8/4441 ,  G06F9/445 ,  G06F9/44505

    Abstract: Methods, systems and devices are disclosed to examine developer supplied graphics code and attributes at run-time. The graphics code designed for execution on a graphics processing unit (GPU) utilizing a coding language such as OpenCL or OpenGL which provides for run-time analysis by a driver, code generator, and compiler. Developer supplied code and attributes can be analyzed and altered based on the execution capabilities and performance criteria of a GPU on which the code is about to be executed. In general, reducing the number of developer defined work items or work groups can reduce the initialization cost of the GPU with respect to the work to be performed and result in an overall optimization of the machine code. Manipulation code can be added to adjust the supplied code in a manner similar to unrolling a loop to improve execution performance.

    Abstract translation: 披露方法，系统和设备，以在运行时检查开发人员提供的图形代码和属性。 设计用于使用诸如OpenCL或OpenGL的编码语言在图形处理单元（GPU）上执行的图形代码，其提供由驱动程序，代码生成器和编译器进行的运行时分析。 开发人员提供的代码和属性可以根据代码即将执行的GPU的执行能力和性能标准进行分析和更改。 通常，减少开发者定义的工作项或工作组的数量可以降低GPU相对于要执行的工作的初始化成本，并导致机器代码的整体优化。 可以添加操作代码以类似于展开循环的方式调整提供的代码，以提高执行性能。

    Processor power and performance manager
    5.
    发明授权
    Processor power and performance manager 有权
    处理器电源和性能管理器

    公开(公告)号：US09329663B2

    公开(公告)日：2016-05-03

    申请号：US14021945

    申请日：2013-09-09

    Applicant: Apple Inc.

    Inventor： Jason Jane ,  Gokhan Avkarogullari ,  Eric Sunalp

    IPC: G06F1/32

    CPC classification number: G06F1/324 ,  G06F1/3206 ,  Y02D10/126

    Abstract: Techniques are provided for managing the power consumption and performance of a processing device. Power consumption and utilization ratios for a processing device may be continuously measured. The measured power consumption and utilization ratios may be compared to target power consumption and utilization ratios to adjust an operating frequency of the processing device. In one implementation a power controller may take the target and measured power consumption as inputs to generate a power output and a utilization controller may take the target and measured utilization ratios as inputs to generate a utilization output. The lower of the power output and the utilization output may be selected and used to adjust the operating frequency of the processing device. The power and utilization controllers may implement a proportional-integral control scheme.

    Abstract translation: 提供了用于管理处理设备的功耗和性能的技术。 可以连续地测量处理装置的功耗和利用率。 可以将测量的功率消耗和利用率与目标功耗和利用率进行比较，以调整处理设备的工作频率。 在一个实现中，功率控制器可以将目标和测量的功率消耗作为输入以产生功率输出，并且利用控制器可以将目标和测量的利用率作为输入以产生利用率输出。 可以选择功率输出和利用率输出的较低者来调整处理装置的工作频率。 电力和利用控制器可以实现比例积分控制方案。

    Displays with Variable Frame Rates
    7.
    发明申请
    Displays with Variable Frame Rates 有权

    公开(公告)号：US20230077843A1

    公开(公告)日：2023-03-16

    申请号：US17887222

    申请日：2022-08-12

    Applicant: Apple Inc.

    Inventor： Wanqing Xin ,  Mehmet N Agaoglu ,  Gokhan Avkarogullari ,  Jenny Hu ,  Alexander K Kan ,  Yuhui Li ,  James R Montgomerie ,  Andrey Pokrovskiy ,  Yingying Tang ,  Chaohao Wang

    IPC: G09G5/36

    Abstract: An electronic device may include a display. Control circuitry may operate the display at different frame rates such as 60 Hz, 80 Hz, and 120 Hz. The control circuitry may determine which frame rate to use based on a speed of animation on the display and based on a type of animation on the display. To mitigate the appearance of judder as the display frame rate changes, the control circuitry may implement techniques such as hysteresis (e.g., windows of tolerance around speed thresholds to ensure that the display frame rate does not change too frequently as a result of noise), speed thresholds that are based on a user perception study, consistent latency between touch input detection and corresponding display output across different frame rates (e.g., using a fixed touch scan rate that is independent of frame duration), and animation-specific speed thresholds for triggering frame rate changes.

    Low latency firmware command selection using a directed acyclic graph
    9.
    发明授权
    Low latency firmware command selection using a directed acyclic graph 有权

    公开(公告)号：US10719970B2

    公开(公告)日：2020-07-21

    申请号：US15864833

    申请日：2018-01-08

    Applicant: Apple Inc.

    Inventor： Kutty Banerjee ,  Rohan Sanjeev Patil ,  Pratik Chandresh Shah ,  Gokhan Avkarogullari ,  Tatsuya Iwamoto

    IPC: G06T15/00 ,  G06T15/80 ,  G06F9/48 ,  G09G5/00

    Abstract: One disclosed embodiment includes a method of scheduling graphics commands for processing. A plurality of micro-commands is generated based on one or more graphics commands obtained from a central processing unit. The dependency between the one or more graphics commands is then determined and an execution graph is generated based on the determined dependency. Each micro-command in the execution graph is connected by an edge to the other micro-commands that it depends on. A wait count is defined for each micro-command of the execution graph, where the wait count indicates the number of micro-commands that the each particular micro-command depends on. One or more micro-commands with a wait count of zero are transmitted to a ready queue for processing.

    Pro-active GPU hardware bootup
    10.
    发明授权
    Pro-active GPU hardware bootup 有权

    公开(公告)号：US10678553B2

    公开(公告)日：2020-06-09

    申请号：US15961086

    申请日：2018-04-24

    Applicant: Apple Inc.

    Inventor： Rohan Sanjeev Patil ,  Gokhan Avkarogullari ,  Tatsuya Iwamoto

    IPC: G06F15/177 ,  G06F9/00 ,  G06F9/4401 ,  G06F1/3206 ,  G06T15/00 ,  G06F9/50 ,  G06T1/20

    Abstract: One disclosed embodiment includes a method of graphics processing. The method includes receiving an indication to update a current frame on a display. A plurality of graphics command are determined to be associated with a next frame that replaces the current frame. A power-up command is generated based on the received indication, configured to cause GPU hardware to begin an initialization operation. The central processing unit processes the plurality of graphics command. Prior to completely process the plurality of graphics command, a power-up command is sent to a GPU firmware. The GPU firmware initializes the GPU hardware based on the power-up command. The processed plurality of graphics command is also transmitted to the GPU hardware. The GPU hardware executes the processed plurality of graphics command to render the next frame on the display.

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