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    Data processing apparatus and method for performing a narrowing-and-rounding arithmetic operation
    31.
    发明授权
    Data processing apparatus and method for performing a narrowing-and-rounding arithmetic operation 有权
    用于执行缩小和舍入算术运算的数据处理装置和方法

    公开(公告)号：US09262123B2

    公开(公告)日：2016-02-16

    申请号：US13955324

    申请日：2013-07-31

    Applicant: ARM LIMITED

    Inventor： Neil Burgess ,  David Raymond Lutz

    IPC: G06F7/50 ,  G06F7/499 ,  G06F7/506

    CPC classification number: G06F7/49947 ,  G06F7/50 ,  G06F7/506

    Abstract: A processing apparatus supports a narrowing-and-rounding arithmetic operation which generates, in response to two operands each comprising at least one W-bit data element, a result value comprising at least one X-bit result data element, with each X-bit result data element representing a sum or difference of corresponding W-bit data elements of the two operands rounded to an X-bit value (W>X). The arithmetic operation is implemented using a number of N-bit additions (N

    Abstract translation: 一种处理装置支持缩小和舍入的算术运算，其响应于每个包括至少一个W位数据元素的两个操作数产生包括至少一个X位结果数据元素的结果值，每个X位 结果数据元素表示舍入到X位值（W> X）的两个操作数的相应W位数据元素的和或差。 使用多个N位加法（N

    Overflow or underflow handling for anchored-data value
    32.
    发明授权
    Overflow or underflow handling for anchored-data value 有权

    公开(公告)号：US10936285B2

    公开(公告)日：2021-03-02

    申请号：US16268692

    申请日：2019-02-06

    Applicant: Arm Limited

    Inventor： David Raymond Lutz ,  Neil Burgess ,  Christopher Neal Hinds

    IPC: G06F7/499 ,  G06F7/48 ,  G06F9/30

    Abstract: Processing circuitry may support processing of anchor-data values comprising one or more anchored-data elements which represent portions of bits of a two's complement number. The anchored-data processing may depend on anchor information indicating at least one property indicative of a numeric range representable by the result anchored-data element or the anchored-data value. When the operation causes an overflow or an underflow, usage information may be stored indicating a cause of the overflow or underflow and/or an indication of how to update the anchor information and/or number of elements in the anchored-data value to prevent the overflow or underflow. This can support dynamic range adjustment in software algorithms which involve anchored-data processing.

    Leading zero anticipation
    33.
    发明授权
    Leading zero anticipation 有权

    公开(公告)号：US10606557B2

    公开(公告)日：2020-03-31

    申请号：US15370212

    申请日：2016-12-06

    Applicant: ARM Limited

    Inventor： David Raymond Lutz

    IPC: G06F7/483 ,  G06F5/01 ,  H03K19/20 ,  G06F7/74

    Abstract: A data processing apparatus is provided. Intermediate value generation circuitry generates an intermediate value from a first floating point number and a second floating point number. The intermediate value includes a number of leading 0s indicative of a prediction of a number of leading 0s in a difference between absolute values of the first floating point number and the second floating point number. The prediction differs by at most one from the number of leading 0s in the difference between absolute values of the first floating point number and the second floating point number. Count circuitry counts the number of leading 0s in said intermediate value and mask generation circuitry produces one or more masks using the intermediate value. The mask generation circuitry produces the one or more masks at the same time or before the count circuitry counts the number of leading 0s in the intermediate value.

    Apparatus and method for processing input operand values
    34.
    发明授权
    Apparatus and method for processing input operand values 有权

    公开(公告)号：US10579338B2

    公开(公告)日：2020-03-03

    申请号：US15833372

    申请日：2017-12-06

    Applicant: ARM Limited

    Inventor： Christopher Neal Hinds ,  Neil Burgess ,  David Raymond Lutz

    IPC: G06F7/57 ,  G06F17/16

    Abstract: An apparatus and method are provided for processing input operand values. The apparatus has a set of vector data storage elements, each vector data storage element providing a plurality of sections for storing data values. A plurality of lanes are considered to be provided within the set of storage elements, where each lane comprises a corresponding section from each vector data storage element. Processing circuitry is arranged to perform an arithmetic operation on an input operand value comprising a plurality of portions, by performing an independent arithmetic operation on each of the plurality of portions, in order to produce a result value comprising a plurality of result portions. Storage circuitry is arranged to store the result value within a selected lane of the plurality of lanes, such that each result portion is stored in a different vector data storage element within the corresponding section for the selected lane. Such an approach allows efficient processing of input operand values in a manner that is not constrained by the size of the vector data storage elements, and in particular in a way that is vector length agnostic.

    Multiply-and-accumulate-products instructions
    35.
    发明授权
    Multiply-and-accumulate-products instructions 有权

    公开(公告)号：US10409592B2

    公开(公告)日：2019-09-10

    申请号：US15494946

    申请日：2017-04-24

    Applicant: ARM LIMITED

    Inventor： Neil Burgess ,  David Raymond Lutz ,  Javier Diaz Bruguera

    IPC: G06F9/30 ,  G06F7/00

    Abstract: An apparatus has processing circuitry comprising an L×M multiplier array. An instruction decoder associated with the processing circuitry supports a multiply-and-accumulate-product (MAP) instruction for generating at least one result element corresponding to a sum of respective E×F products of E-bit and F-bit portions of J-bit and K-bit operands respectively, where 1

    Apparatus and method for supporting a conversion instruction
    36.
    发明授权
    Apparatus and method for supporting a conversion instruction 有权

    公开(公告)号：US10310809B2

    公开(公告)日：2019-06-04

    申请号：US15093947

    申请日：2016-04-08

    Applicant: ARM LIMITED

    Inventor： David Raymond Lutz ,  Neil Burgess ,  Kelvin Domnic Goveas

    IPC: G06F5/01 ,  G06F9/30 ,  H03M7/24 ,  G06F7/483

    Abstract: A data processing system includes instruction decoder circuitry responsive to a conversion instruction FCVTJS to convert a double precision floating point number into a 32-bit integer number. Right shifting circuitry performs a right shift upon at least part of the input number and left shifting circuitry performs a left shift of at least part of the input number. Selection circuitry serves to select one of the right shifted number and the left shifted number as a selected shifted number which forms at least part of the output number which is generated.

    Apparatus and method for fixed point to floating point conversion and negative power of two detector
    37.
    发明授权
    Apparatus and method for fixed point to floating point conversion and negative power of two detector 有权

    公开(公告)号：US10019231B2

    公开(公告)日：2018-07-10

    申请号：US15242782

    申请日：2016-08-22

    Applicant: ARM LIMITED

    Inventor： David Raymond Lutz

    IPC: G06F9/30 ,  G06F7/483

    CPC classification number: G06F7/483 ,  G06F7/49936

    Abstract: A data processing system 2 supports conversion of fixed point numbers to floating point numbers. The result floating point numbers may be subnormal. A first shifter 28 shifts input signals representing the fixed point number by a first shift amount depending upon a leading zero count within an integer portion followed by a fractional portion of the fixed point number. A second shifter 30 shifts the input signals by a second shift amount depending upon the variable point position within the fixed point number. A subnormal result detector 34 generates a selection signal in dependence upon detection of a combination of a variable point position and the count of leading zeros which corresponds to the floating point number having a subnormal value. Selection circuitry 32 selects one of the outputs from the first shifter or the second shifter to form the significand in dependence upon the selection signal generated by the subnormal result detector.

    Multiply adder
    40.
    发明授权
    Multiply adder 有权

    公开(公告)号：US09696964B2

    公开(公告)日：2017-07-04

    申请号：US14566981

    申请日：2014-12-11

    Applicant: ARM LIMITED

    Inventor： David Raymond Lutz ,  Neil Burgess

    IPC: G06F7/544 ,  G06F7/483

    CPC classification number: G06F7/5443 ,  G06F7/483

    Abstract: A floating point multiply add circuit 24 includes a multiplier 26 and an adder 28. The input operands A, B and C together with the result value all have a normal exponent value range, such as a range consistent with the IEEE Standard 754. The product value which is passed from the multiplier 26 to the adder 28 as an extended exponent value range that extents lower than the normal exponent value range. Shifters 48, 50 within the adder can take account of the extended exponent value range of the product as necessary in order to bring the result value back into the normal exponent value range.

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